Merge pull request #804 from aguinet/feature/arm_svc

Support of ARM SVC in the Miasm VM

4 files changed, 42 insertions, 7 deletions

diff --git a/miasm2/arch/arm/regs.py b/miasm2/arch/arm/regs.py
index dce4cb98..e20b00bd 100644
--- a/miasm2/arch/arm/regs.py
+++ b/miasm2/arch/arm/regs.py
@@ -9,6 +9,7 @@ regs32_str = ["R%d" % i for i in xrange(13)] + ["SP", "LR", "PC"]
 regs32_expr = [ExprId(x, 32) for x in regs32_str]
 
 exception_flags = ExprId('exception_flags', 32)
+interrupt_num = ExprId('interrupt_num', 32)
 bp_num = ExprId('bp_num', 32)
 
 
@@ -84,7 +85,7 @@ all_regs_ids = [
     R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, SP, LR, PC,
     zf, nf, of, cf,
     ge0, ge1, ge2, ge3,
-    exception_flags, bp_num
+    exception_flags, interrupt_num, bp_num
 ]
 
 all_regs_ids_no_alias = all_regs_ids
@@ -102,7 +103,7 @@ all_regs_ids_init = [R0_init, R1_init, R2_init, R3_init,
                      R12_init, SP_init, LR_init, PC_init,
                      zf_init, nf_init, of_init, cf_init,
                      ge0_init, ge1_init, ge2_init, ge3_init,
-                     ExprInt(0, 32), ExprInt(0, 32)
+                     ExprInt(0, 32), ExprInt(0, 32), ExprInt(0, 32)
                      ]
 
 regs_init = {}
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index 00250157..d9c2d6cd 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -3,7 +3,7 @@ from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock
 from miasm2.arch.arm.arch import mn_arm, mn_armt
 from miasm2.arch.arm.regs import *
 
-from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO
+from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO, EXCEPT_INT_XX
 
 # liris.cnrs.fr/~mmrissa/lib/exe/fetch.php?media=armv7-a-r-manual.pdf
 EXCEPT_SOFT_BP = (1 << 1)
@@ -805,9 +805,10 @@ def stmdb(ir, instr, a, b):
 
 
 def svc(ir, instr, a):
-    # XXX TODO implement
-    e = [
-        ExprAff(exception_flags, ExprInt(EXCEPT_PRIV_INSN, 32))]
+    e = []
+    except_int = EXCEPT_INT_XX
+    e.append(ExprAff(exception_flags, ExprInt(except_int, 32)))
+    e.append(ExprAff(interrupt_num, a))
     return e, []
 
 
diff --git a/miasm2/jitter/arch/JitCore_arm.c b/miasm2/jitter/arch/JitCore_arm.c
index c71db0c6..f253c45b 100644
--- a/miasm2/jitter/arch/JitCore_arm.c
+++ b/miasm2/jitter/arch/JitCore_arm.c
@@ -38,6 +38,9 @@ reg_dict gpreg_dict[] = { {.name = "R0", .offset = offsetof(vm_cpu_t, R0)},
 			  {.name = "ge1", .offset = offsetof(vm_cpu_t, ge1)},
 			  {.name = "ge2", .offset = offsetof(vm_cpu_t, ge2)},
 			  {.name = "ge3", .offset = offsetof(vm_cpu_t, ge3)},
+
+        {.name = "exception_flags", .offset = offsetof(vm_cpu_t, exception_flags)},
+        {.name = "interrupt_num", .offset = offsetof(vm_cpu_t, interrupt_num)},
 };
 
 /************************** JitCpu object **************************/
@@ -243,6 +246,26 @@ PyObject* vm_set_mem(JitCpu *self, PyObject* args)
        return Py_None;
 }
 
+PyObject* cpu_set_interrupt_num(JitCpu* self, PyObject* args)
+{
+	PyObject *item1;
+	uint64_t i;
+
+	if (!PyArg_ParseTuple(args, "O", &item1))
+		RAISE(PyExc_TypeError,"Cannot parse arguments");
+
+	PyGetInt(item1, i);
+
+	((vm_cpu_t*)self->cpu)->interrupt_num = i;
+	Py_INCREF(Py_None);
+	return Py_None;
+}
+
+PyObject* cpu_get_interrupt_num(JitCpu* self, PyObject* args)
+{
+	return PyLong_FromUnsignedLongLong((uint64_t)(((vm_cpu_t*)self->cpu)->interrupt_num));
+}
+
 static PyMemberDef JitCpu_members[] = {
     {NULL}  /* Sentinel */
 };
@@ -260,6 +283,10 @@ static PyMethodDef JitCpu_methods[] = {
 	 "X"},
 	{"set_exception", (PyCFunction)cpu_set_exception, METH_VARARGS,
 	 "X"},
+	{"get_interrupt_num", (PyCFunction)cpu_get_interrupt_num, METH_VARARGS,
+	 "X"},
+	{"set_interrupt_num", (PyCFunction)cpu_set_interrupt_num, METH_VARARGS,
+	 "X"},
 	{"set_mem", (PyCFunction)vm_set_mem, METH_VARARGS,
 	 "X"},
 	{"get_mem", (PyCFunction)vm_get_mem, METH_VARARGS,
@@ -305,6 +332,8 @@ getset_reg_u32(ge1);
 getset_reg_u32(ge2);
 getset_reg_u32(ge3);
 
+getset_reg_u32(exception_flags);
+getset_reg_u32(interrupt_num);
 
 PyObject* get_gpreg_offset_all(void)
 {
@@ -312,6 +341,7 @@ PyObject* get_gpreg_offset_all(void)
     PyObject *o;
 
     get_reg_off(exception_flags);
+    get_reg_off(interrupt_num);
 
     get_reg_off(R0);
     get_reg_off(R1);
@@ -344,7 +374,6 @@ PyObject* get_gpreg_offset_all(void)
     return dict;
 }
 
-
 static PyGetSetDef JitCpu_getseters[] = {
     {"vmmngr",
      (getter)JitCpu_get_vmmngr, (setter)JitCpu_set_vmmngr,
@@ -385,6 +414,9 @@ static PyGetSetDef JitCpu_getseters[] = {
     {"ge2", (getter)JitCpu_get_ge2, (setter)JitCpu_set_ge2, "ge2", NULL},
     {"ge3", (getter)JitCpu_get_ge3, (setter)JitCpu_set_ge3, "ge3", NULL},
 
+    {"exception_flags", (getter)JitCpu_get_exception_flags, (setter)JitCpu_set_exception_flags, "exception_flags", NULL},
+    {"interrupt_num", (getter)JitCpu_get_interrupt_num, (setter)JitCpu_set_interrupt_num, "interrupt_num", NULL},
+
     {NULL}  /* Sentinel */
 };
 
diff --git a/miasm2/jitter/arch/JitCore_arm.h b/miasm2/jitter/arch/JitCore_arm.h
index 1f3ccaf2..abd821db 100644
--- a/miasm2/jitter/arch/JitCore_arm.h
+++ b/miasm2/jitter/arch/JitCore_arm.h
@@ -1,6 +1,7 @@
 
 typedef struct {
 	uint32_t exception_flags;
+	uint32_t interrupt_num;
 
 	/* gpregs */
 	uint32_t R0;