Merge pull request #922 from serpilliere/updt_aarch64_mn

Updt aarch64 mn

3 files changed, 100 insertions, 0 deletions

diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py
index 38cffc47..91554233 100644
--- a/miasm2/arch/aarch64/arch.py
+++ b/miasm2/arch/aarch64/arch.py
@@ -2155,3 +2155,9 @@ aarch64op("stlxp", [bs('1'), sf, bs('001000'), bs('0'), bs('0'), bs('1'), rs32,
 aarch64op("dsb", [bs('1101010100'), bs('0000110011'), crm, bs('1'), bs('00'), bs('11111')], [crm])
 aarch64op("dmb", [bs('1101010100'), bs('0000110011'), crm, bs('1'), bs('01'), bs('11111')], [crm])
 aarch64op("isb", [bs('1101010100'), bs('0000110011'), crm, bs('1'), bs('10'), bs('11111')], [crm])
+
+stacctype = bs_mod_name(l=1, fname='order', mn_mod=['', 'L'])
+ltacctype = bs_mod_name(l=1, fname='order', mn_mod=['', 'A'])
+
+
+aarch64op("casp",   [bs('0'), sf, bs('001000'), bs('0'), ltacctype, bs('1'), rs, stacctype, bs('11111'), rn64_deref_nooff, rt], [rs, rt, rn64_deref_nooff])
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py
index 8451d3e9..f22f0c07 100644
--- a/miasm2/arch/aarch64/sem.py
+++ b/miasm2/arch/aarch64/sem.py
@@ -1200,6 +1200,74 @@ def clz(ir, instr, arg1, arg2):
     e.append(ExprAssign(arg1, ExprOp('cntleadzeros', arg2)))
     return e, []
 
+def casp(ir, instr, arg1, arg2, arg3):
+    # XXX TODO: memory barrier
+    e = []
+    if arg1.size == 32:
+        regs = gpregs32_expr
+    else:
+        regs = gpregs64_expr
+    index1 = regs.index(arg1)
+    index2 = regs.index(arg2)
+
+    # TODO endianness
+    comp_value = ExprCompose(regs[index1], regs[index1 + 1])
+    new_value = ExprCompose(regs[index2], regs[index2 + 1])
+    assert arg3.is_op('preinc')
+    ptr = arg3.args[0]
+    data = ExprMem(ptr, comp_value.size)
+
+    loc_store = ExprLoc(ir.loc_db.add_location(), ir.IRDst.size)
+    loc_do = ExprLoc(ir.loc_db.add_location(), ir.IRDst.size)
+    loc_next = ExprLoc(ir.get_next_loc_key(instr), ir.IRDst.size)
+
+    e.append(ExprAssign(ir.IRDst, ExprCond(ExprOp("FLAG_EQ_CMP", data, comp_value), loc_do, loc_store)))
+
+    e_store = []
+    e_store.append(ExprAssign(data, new_value))
+    e_store.append(ExprAssign(ir.IRDst, loc_do))
+    blk_store = IRBlock(loc_store.loc_key, [AssignBlock(e_store, instr)])
+
+    e_do = []
+    e_do.append(ExprAssign(regs[index1], data[:data.size / 2]))
+    e_do.append(ExprAssign(regs[index1 + 1], data[data.size / 2:]))
+    e_do.append(ExprAssign(ir.IRDst, loc_next))
+    blk_do = IRBlock(loc_do.loc_key, [AssignBlock(e_do, instr)])
+
+    return e, [blk_store, blk_do]
+
+
+@sbuild.parse
+def umaddl(arg1, arg2, arg3, arg4):
+    arg1 = arg2.zeroExtend(arg1.size) * arg3.zeroExtend(arg1.size) + arg4
+
+
+@sbuild.parse
+def umsubbl(arg1, arg2, arg3, arg4):
+    arg1 = arg2.zeroExtend(arg1.size) * arg3.zeroExtend(arg1.size) + arg4
+
+
+@sbuild.parse
+def umull(arg1, arg2, arg3):
+    arg1 = (arg2.zeroExtend(64) * arg3.zeroExtend(64))
+
+
+@sbuild.parse
+def umulh(arg1, arg2, arg3):
+    arg1 = (arg2.zeroExtend(128) * arg3.zeroExtend(128))[64:]
+
+
+@sbuild.parse
+def smulh(arg1, arg2, arg3):
+    arg1 = (arg2.signExtend(128) * arg3.signExtend(128))[64:]
+
+
+@sbuild.parse
+def smull(arg1, arg2, arg3):
+    arg1 = (arg2.signExtend(64) * arg3.signExtend(64))[64:]
+
+
+
 mnemo_func = sbuild.functions
 mnemo_func.update({
     'and': and_l,
@@ -1292,6 +1360,12 @@ mnemo_func.update({
     'fcmpe': fcmpe,
     'clz': clz,
 
+    # XXX TODO: memory barrier
+    'casp':casp,
+    'caspl':casp,
+    'caspa':casp,
+    'caspal':casp,
+
 
 })
 
diff --git a/test/arch/aarch64/arch.py b/test/arch/aarch64/arch.py
index cba175e6..46a4514b 100644
--- a/test/arch/aarch64/arch.py
+++ b/test/arch/aarch64/arch.py
@@ -7,6 +7,7 @@ from miasm2.core.locationdb import LocationDB
 loc_db = LocationDB()
 
 reg_tests_aarch64 = [
+
     ("XXXXXXXX    MOV        W1, WZR",
      "E1031F2A"),
     ("XXXXXXXX    TST        W5, W3",
@@ -1794,6 +1795,25 @@ reg_tests_aarch64 = [
     ("XXXXXXXX    ORR        X8, 0x0, 0x1000100010001",
      "E88300B2"),
 
+
+    ("XXXXXXXX    CASP       X0, X2, [X4]",
+     "827C2048"),
+    ("XXXXXXXX    CASPL      X0, X2, [X4]",
+     "82FC2048"),
+    ("XXXXXXXX    CASPA      X0, X2, [X4]",
+     "827C6048"),
+    ("XXXXXXXX    CASPAL     X0, X2, [X4]",
+     "82FC6048"),
+
+    ("XXXXXXXX    CASP       W0, W2, [X4]",
+     "827C2008"),
+    ("XXXXXXXX    CASPL      W0, W2, [X4]",
+     "82FC2008"),
+    ("XXXXXXXX    CASPA      W0, W2, [X4]",
+     "827C6008"),
+    ("XXXXXXXX    CASPAL     W0, W2, [X4]",
+     "82FC6008"),
+
 ]