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| author | serpilliere <serpilliere@users.noreply.github.com> | 2020-06-09 17:21:16 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-09 17:21:16 +0200 |
| commit | 5b77d04ec1ca533948d0a69f3c41efaf91cc3e9c (patch) | |
| tree | 6622ddf8b0ae966ec008d202fb6a9581a40339da | |
| parent | 6faf83fe27bbfc7fec501d9b674480f02edea854 (diff) | |
| parent | a3ccfd025231c4620a0d252f5e6b138a898dbece (diff) | |
| download | focaccia-miasm-5b77d04ec1ca533948d0a69f3c41efaf91cc3e9c.tar.gz focaccia-miasm-5b77d04ec1ca533948d0a69f3c41efaf91cc3e9c.zip | |
Merge pull request #1250 from serpilliere/fix_x86_sem
Updt x86 swap 16 bit
| -rw-r--r-- | miasm/arch/x86/sem.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/miasm/arch/x86/sem.py b/miasm/arch/x86/sem.py index b0fcd054..86a933a0 100644 --- a/miasm/arch/x86/sem.py +++ b/miasm/arch/x86/sem.py @@ -1162,7 +1162,9 @@ def setalc(_, instr): def bswap(_, instr, dst): e = [] if dst.size == 16: - result = m2_expr.ExprCompose(dst[8:16], dst[:8]) + # BSWAP referencing a 16-bit register is undefined + # Seems to return 0 actually + result = m2_expr.ExprInt(0, 16) elif dst.size == 32: result = m2_expr.ExprCompose( dst[24:32], dst[16:24], dst[8:16], dst[:8]) |