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authorFabrice Desclaux <fabrice.desclaux@cea.fr>2018-06-22 19:49:09 +0200
committerFabrice Desclaux <fabrice.desclaux@cea.fr>2018-07-05 16:14:26 +0200
commit195c688da01add6d4d964addfe7e34bea78bdb03 (patch)
tree80b346193da5609d19cdfc389ea84ad66399fa67 /example/symbol_exec/single_instr.py
parent3e86fb7046eef0adef023207cb4875174b26beea (diff)
downloadfocaccia-miasm-195c688da01add6d4d964addfe7e34bea78bdb03.tar.gz
focaccia-miasm-195c688da01add6d4d964addfe7e34bea78bdb03.zip
IR: gen ircfg from ir_arch
Diffstat (limited to 'example/symbol_exec/single_instr.py')
-rw-r--r--example/symbol_exec/single_instr.py5
1 files changed, 3 insertions, 2 deletions
diff --git a/example/symbol_exec/single_instr.py b/example/symbol_exec/single_instr.py
index 6ddd2608..c78f1f7f 100644
--- a/example/symbol_exec/single_instr.py
+++ b/example/symbol_exec/single_instr.py
@@ -21,14 +21,15 @@ asm_block = mdis.dis_block(START_ADDR)
 
 # Translate ASM -> IR
 ira = machine.ira(mdis.loc_db)
-ira.add_block(asm_block)
+ircfg = ira.new_ircfg()
+ira.add_asmblock_to_ircfg(asm_block, ircfg)
 
 # Instanciate a Symbolic Execution engine with default value for registers
 symb = SymbolicExecutionEngine(ira)
 
 # Emulate one IR basic block
 ## Emulation of several basic blocks can be done through .emul_ir_blocks
-cur_addr = symb.run_at(START_ADDR)
+cur_addr = symb.run_at(ircfg, START_ADDR)
 
 # Modified elements
 print 'Modified registers:'