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| author | William Bruneau <william.bruneau@epfedu.fr> | 2019-04-05 12:14:39 +0200 |
|---|---|---|
| committer | serpilliere <serpilliere@users.noreply.github.com> | 2019-04-05 12:14:39 +0200 |
| commit | 57ab3d0fc327f23f995ea6000d1077c3f749ef20 (patch) | |
| tree | 5cf423e257a8dafc7629a45e74ed7ec9401a227a /miasm/arch/x86/arch.py | |
| parent | d5ed94165c1143b75185ab80f330df1ca6d94b5a (diff) | |
| download | focaccia-miasm-57ab3d0fc327f23f995ea6000d1077c3f749ef20.tar.gz focaccia-miasm-57ab3d0fc327f23f995ea6000d1077c3f749ef20.zip | |
Add CET instructions (#1003)
* Add CET instructions * Fix RDSSP
Diffstat (limited to 'miasm/arch/x86/arch.py')
| -rw-r--r-- | miasm/arch/x86/arch.py | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/miasm/arch/x86/arch.py b/miasm/arch/x86/arch.py index a82fac02..3053301a 100644 --- a/miasm/arch/x86/arch.py +++ b/miasm/arch/x86/arch.py @@ -3212,6 +3212,14 @@ class bs_mem(object): self.value = v return v != 0b11 +class bs_reg(object): + def encode(self): + return self.value == 0b11 + + def decode(self, v): + self.value = v + return v == 0b11 + d_imm64 = bs(l=0, fname="imm64") d_eax = bs(l=0, cls=(bs_eax, ), fname='eax') @@ -3239,6 +3247,7 @@ msegoff = bs(l=16, cls=(bs_msegoff,), fname="mseg") movoff = bs(l=0, cls=(bs_movoff,), fname="off") mod = bs(l=2, fname="mod") mod_mem = bs(l=2, cls=(bs_mem,), fname="mod") +mod_reg = bs(l=2, cls=(bs_reg,), fname="mod") rmreg = bs(l=3, cls=(x86_rm_reg, ), order =1, fname = "reg") reg = bs(l=3, cls=(x86_reg, ), order =1, fname = "reg") @@ -3721,7 +3730,7 @@ addop("lgs", [bs8(0x0f), bs8(0xb5)] + rmmod(rmreg, rm_arg_x=rm_mem, modrm=mod_me addop("lgdt", [bs8(0x0f), bs8(0x01)] + rmmod(d2, modrm=mod_mem)) addop("lidt", [bs8(0x0f), bs8(0x01)] + rmmod(d3, modrm=mod_mem)) -addop("lfence", [bs8(0x0f), bs8(0xae), bs8(0xe8)]) +addop("lfence", [bs8(0x0f), bs8(0xae), bs8(0xe8), no_xmm_pref]) addop("mfence", [bs8(0x0f), bs8(0xae), bs8(0xf0)]) addop("sfence", [bs8(0x0f), bs8(0xae), bs8(0xf8)]) @@ -4620,6 +4629,14 @@ addop("maskmovdqu", [bs8(0x0f), bs8(0xf7), pref_66] + addop("emms", [bs8(0x0f), bs8(0x77)]) +addop("incssp", [pref_f3, bs8(0x0f), bs8(0xae)] + rmmod(d5)) +addop("rdssp", [pref_f3, bs8(0x0f), bs8(0x1e)] + rmmod(d1, modrm=mod_reg)) +addop("saveprevssp", [pref_f3, bs8(0x0f), bs8(0x01), bs8(0xea)]) +addop("rstorssp", [pref_f3, bs8(0x0f), bs8(0x01)] + rmmod(d5, rm_arg_xmm, modrm=mod_mem)) +addop("wrss", [bs8(0x0f), bs8(0x38), bs8(0xf6)] + rmmod(rmreg, rm_arg), [rm_arg, rmreg]) +addop("wruss", [pref_66, bs8(0x0f), bs8(0x38), bs8(0xf5)] + rmmod(rmreg, rm_arg), [rm_arg, rmreg]) +addop("setssbsy", [pref_f3, bs8(0x0f), bs8(0x01), bs8(0xe8)]) +addop("clrssbsy", [pref_f3, bs8(0x0f), bs8(0xae)] + rmmod(d6, rm_arg_xmm)) addop("endbr64", [pref_f3, bs8(0x0f), bs8(0x1e), bs8(0xfa)]) addop("endbr32", [pref_f3, bs8(0x0f), bs8(0x1e), bs8(0xfb)]) |