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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2020-12-25 22:23:01 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2020-12-25 22:23:01 +0100 |
| commit | 1d95a7febaee8c53df432cdbf1539f6f58a4d5d9 (patch) | |
| tree | 4afb9c40cc0aad93a3a5d26bb84f487da5a667e2 /miasm/jitter/jitcore_llvm.py | |
| parent | 972cad3a89d2856a6969328a9870a1b472cd9fd2 (diff) | |
| download | focaccia-miasm-1d95a7febaee8c53df432cdbf1539f6f58a4d5d9.tar.gz focaccia-miasm-1d95a7febaee8c53df432cdbf1539f6f58a4d5d9.zip | |
Rename ir_arch for jitter
Diffstat (limited to 'miasm/jitter/jitcore_llvm.py')
| -rw-r--r-- | miasm/jitter/jitcore_llvm.py | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/miasm/jitter/jitcore_llvm.py b/miasm/jitter/jitcore_llvm.py index df7d5950..4f1871b2 100644 --- a/miasm/jitter/jitcore_llvm.py +++ b/miasm/jitter/jitcore_llvm.py @@ -28,8 +28,8 @@ class JitCore_LLVM(jitcore.JitCore): "ppc32": "JitCore_ppc32", } - def __init__(self, ir_arch, bin_stream): - super(JitCore_LLVM, self).__init__(ir_arch, bin_stream) + def __init__(self, lifter, bin_stream): + super(JitCore_LLVM, self).__init__(lifter, bin_stream) self.options.update( { @@ -41,7 +41,7 @@ class JitCore_LLVM(jitcore.JitCore): ) self.exec_wrapper = Jitllvm.llvm_exec_block - self.ir_arch = ir_arch + self.lifter = lifter # Cache temporary dir self.tempdir = os.path.join(tempfile.gettempdir(), "miasm_cache") @@ -72,23 +72,23 @@ class JitCore_LLVM(jitcore.JitCore): lib_dir = os.path.join(lib_dir, 'arch') try: jit_lib = os.path.join( - lib_dir, self.arch_dependent_libs[self.ir_arch.arch.name] + ext + lib_dir, self.arch_dependent_libs[self.lifter.arch.name] + ext ) libs_to_load.append(jit_lib) except KeyError: pass # Create a context - self.context = LLVMContext_JIT(libs_to_load, self.ir_arch) + self.context = LLVMContext_JIT(libs_to_load, self.lifter) # Set the optimisation level self.context.optimise_level() # Save the current architecture parameters - self.arch = self.ir_arch.arch + self.arch = self.lifter.arch # Get the correspondence between registers and vmcpu struct - mod_name = "miasm.jitter.arch.JitCore_%s" % (self.ir_arch.arch.name) + mod_name = "miasm.jitter.arch.JitCore_%s" % (self.lifter.arch.name) mod = importlib.import_module(mod_name) self.context.set_vmcpu(mod.get_gpreg_offset_all()) @@ -140,5 +140,5 @@ class JitCore_LLVM(jitcore.JitCore): # Store a pointer on the function jitted code loc_key = block.loc_key - offset = self.ir_arch.loc_db.get_location_offset(loc_key) + offset = self.lifter.loc_db.get_location_offset(loc_key) self.offset_to_jitted_func[offset] = ptr |