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-rw-r--r--miasm2/arch/x86/regs.py11
-rw-r--r--miasm2/arch/x86/sem.py9
-rw-r--r--miasm2/jitter/arch/JitCore_x86.c18
-rw-r--r--miasm2/jitter/arch/JitCore_x86.h3
4 files changed, 14 insertions, 27 deletions
diff --git a/miasm2/arch/x86/regs.py b/miasm2/arch/x86/regs.py
index 84590c75..ef1095e2 100644
--- a/miasm2/arch/x86/regs.py
+++ b/miasm2/arch/x86/regs.py
@@ -235,9 +235,7 @@ reg_mm5 = 'MM5'
 reg_mm6 = 'MM6'
 reg_mm7 = 'MM7'
 
-
-reg_tsc1 = "tsc1"
-reg_tsc2 = "tsc2"
+reg_tsc = "tsc"
 
 reg_float_c0 = 'float_c0'
 reg_float_c1 = 'float_c1'
@@ -321,8 +319,7 @@ DS = ExprId(reg_ds, size=16)
 FS = ExprId(reg_fs, size=16)
 GS = ExprId(reg_gs, size=16)
 
-tsc1 = ExprId(reg_tsc1, size=32)
-tsc2 = ExprId(reg_tsc2, size=32)
+tsc = ExprId(reg_tsc, size=64)
 
 float_c0 = ExprId(reg_float_c0, size=1)
 float_c1 = ExprId(reg_float_c1, size=1)
@@ -388,7 +385,7 @@ all_regs_ids = [
     zf, nf, pf, of, cf, af, df,
     tf, i_f, iopl, nt, rf, vm, ac, vif, vip, i_d,
     float_control, float_eip, float_cs, float_address, float_ds,
-    tsc1, tsc2,
+    tsc,
     ES, CS, SS, DS, FS, GS,
     float_st0, float_st1, float_st2, float_st3,
     float_st4, float_st5, float_st6, float_st7,
@@ -411,7 +408,7 @@ all_regs_ids_no_alias = [
     zf, nf, pf, of, cf, af, df,
     tf, i_f, iopl, nt, rf, vm, ac, vif, vip, i_d,
     float_control, float_eip, float_cs, float_address, float_ds,
-    tsc1, tsc2,
+    tsc,
     ES, CS, SS, DS, FS, GS,
     float_st0, float_st1, float_st2, float_st3,
     float_st4, float_st5, float_st6, float_st7,
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index b2ef5a43..d03a7cd4 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -3040,12 +3040,9 @@ def hlt(_, instr):
 
 def rdtsc(_, instr):
     e = []
-    e.append(m2_expr.ExprAssign(tsc1, tsc1 + m2_expr.ExprInt(1, 32)))
-    e.append(m2_expr.ExprAssign(tsc2, tsc2 + m2_expr.ExprCond(tsc1 - tsc1.mask,
-                                                           m2_expr.ExprInt(0, 32),
-                                                           m2_expr.ExprInt(1, 32))))
-    e.append(m2_expr.ExprAssign(mRAX[32], tsc1))
-    e.append(m2_expr.ExprAssign(mRDX[32], tsc2))
+    e.append(m2_expr.ExprAssign(tsc, tsc + m2_expr.ExprInt(1, 64)))
+    e.append(m2_expr.ExprAssign(mRAX[32], tsc[:32]))
+    e.append(m2_expr.ExprAssign(mRDX[32], tsc[32:]))
     return e, []
 
 
diff --git a/miasm2/jitter/arch/JitCore_x86.c b/miasm2/jitter/arch/JitCore_x86.c
index fa47b324..a13b6881 100644
--- a/miasm2/jitter/arch/JitCore_x86.c
+++ b/miasm2/jitter/arch/JitCore_x86.c
@@ -74,8 +74,7 @@ reg_dict gpreg_dict[] = {
 			 {.name = "XMM14", .offset = offsetof(vm_cpu_t, XMM14), .size = 128},
 			 {.name = "XMM15", .offset = offsetof(vm_cpu_t, XMM15), .size = 128},
 
-			 {.name = "tsc1", .offset = offsetof(vm_cpu_t, tsc1), .size = 32},
-			 {.name = "tsc2", .offset = offsetof(vm_cpu_t, tsc2), .size = 32},
+			 {.name = "tsc", .offset = offsetof(vm_cpu_t, tsc), .size = 64},
 
 			 {.name = "exception_flags", .offset = offsetof(vm_cpu_t, exception_flags), .size = 32},
 			 {.name = "interrupt_num", .offset = offsetof(vm_cpu_t, interrupt_num), .size = 32},
@@ -156,8 +155,7 @@ PyObject* cpu_get_gpreg(JitCpu* self)
     get_reg_bn(XMM14, 128);
     get_reg_bn(XMM15, 128);
 
-    get_reg(tsc1);
-    get_reg(tsc2);
+    get_reg(tsc);
 
     return dict;
 }
@@ -266,8 +264,7 @@ PyObject* cpu_set_gpreg(JitCpu* self, PyObject *args)
 PyObject * cpu_init_regs(JitCpu* self)
 {
 	memset(self->cpu, 0, sizeof(vm_cpu_t));
-	((vm_cpu_t*)self->cpu)->tsc1 = 0x22222222;
-	((vm_cpu_t*)self->cpu)->tsc2 = 0x11111111;
+	((vm_cpu_t*)self->cpu)->tsc = 0x1122334455667788ULL;
 	((vm_cpu_t*)self->cpu)->i_f = 1;
 	Py_INCREF(Py_None);
 	return Py_None;
@@ -662,8 +659,7 @@ getset_reg_bn(XMM13, 128);
 getset_reg_bn(XMM14, 128);
 getset_reg_bn(XMM15, 128);
 
-getset_reg_u32(tsc1);
-getset_reg_u32(tsc2);
+getset_reg_u64(tsc);
 
 getset_reg_u32(exception_flags);
 getset_reg_u32(interrupt_num);
@@ -754,8 +750,7 @@ PyObject* get_gpreg_offset_all(void)
     get_reg_off(XMM14);
     get_reg_off(XMM15);
 
-    get_reg_off(tsc1);
-    get_reg_off(tsc2);
+    get_reg_off(tsc);
 
     get_reg_off(interrupt_num);
     get_reg_off(exception_flags);
@@ -859,8 +854,7 @@ static PyGetSetDef JitCpu_getseters[] = {
     {"XMM14", (getter)JitCpu_get_XMM14, (setter)JitCpu_set_XMM14, "XMM14", NULL},
     {"XMM15", (getter)JitCpu_get_XMM15, (setter)JitCpu_set_XMM15, "XMM15", NULL},
 
-    {"tsc1", (getter)JitCpu_get_tsc1, (setter)JitCpu_set_tsc1, "tsc1", NULL},
-    {"tsc2", (getter)JitCpu_get_tsc2, (setter)JitCpu_set_tsc2, "tsc2", NULL},
+    {"tsc", (getter)JitCpu_get_tsc, (setter)JitCpu_set_tsc, "tsc", NULL},
 
     {"exception_flags", (getter)JitCpu_get_exception_flags, (setter)JitCpu_set_exception_flags, "exception_flags", NULL},
     {"interrupt_num", (getter)JitCpu_get_interrupt_num, (setter)JitCpu_set_interrupt_num, "interrupt_num", NULL},
diff --git a/miasm2/jitter/arch/JitCore_x86.h b/miasm2/jitter/arch/JitCore_x86.h
index 6d86d6b8..27d94d7c 100644
--- a/miasm2/jitter/arch/JitCore_x86.h
+++ b/miasm2/jitter/arch/JitCore_x86.h
@@ -80,8 +80,7 @@ typedef struct {
 	unsigned int reg_float_ds;
 
 
-	uint64_t tsc1;
-	uint64_t tsc2;
+	uint64_t tsc;
 
 
 	uint16_t ES;