diff options
| -rw-r--r-- | miasm2/ir/translators/z3_ir.py | 12 | ||||
| -rw-r--r-- | miasm2/jitter/vm_mngr.h | 2 |
2 files changed, 13 insertions, 1 deletions
diff --git a/miasm2/ir/translators/z3_ir.py b/miasm2/ir/translators/z3_ir.py index d33764fb..74bdd79c 100644 --- a/miasm2/ir/translators/z3_ir.py +++ b/miasm2/ir/translators/z3_ir.py @@ -1,7 +1,9 @@ +import imp import logging import operator -import z3 +# Raise an ImportError if z3 is not available WITHOUT actually importing it +imp.find_module("z3") from miasm2.core.asmblock import AsmLabel from miasm2.ir.translators.translator import Translator @@ -31,6 +33,10 @@ class Z3Mem(object): @name: name of memory Arrays generated. They will be named name+str(address size) (for example mem32, mem16...). """ + # Import z3 only on demand + global z3 + import z3 + if endianness not in ['<', '>']: raise ValueError("Endianness should be '>' (big) or '<' (little)") self.endianness = endianness @@ -114,6 +120,10 @@ class TranslatorZ3(Translator): """Instance a Z3 translator @endianness: (optional) memory endianness """ + # Import z3 only on demand + global z3 + import z3 + super(TranslatorZ3, self).__init__(**kwargs) self._mem = Z3Mem(endianness) diff --git a/miasm2/jitter/vm_mngr.h b/miasm2/jitter/vm_mngr.h index 71ecc246..d114d8f0 100644 --- a/miasm2/jitter/vm_mngr.h +++ b/miasm2/jitter/vm_mngr.h @@ -217,6 +217,8 @@ unsigned int umul16_hi(unsigned short a, unsigned short b); uint64_t rot_left(uint64_t size, uint64_t a, uint64_t b); uint64_t rot_right(uint64_t size, uint64_t a, uint64_t b); +unsigned int x86_bsr(uint64_t size, uint64_t src); +unsigned int x86_bsf(uint64_t size, uint64_t src); #define UDIV(sizeA) \ uint ## sizeA ## _t udiv ## sizeA (vm_cpu_t* vmcpu, uint ## sizeA ## _t a, uint ## sizeA ## _t b) \ |