diff options
Diffstat (limited to 'miasm/arch')
| -rw-r--r-- | miasm/arch/arm/jit.py | 6 | ||||
| -rw-r--r-- | miasm/arch/mep/jit.py | 12 | ||||
| -rw-r--r-- | miasm/arch/mips32/jit.py | 14 | ||||
| -rw-r--r-- | miasm/arch/x86/jit.py | 48 |
4 files changed, 40 insertions, 40 deletions
diff --git a/miasm/arch/arm/jit.py b/miasm/arch/arm/jit.py index 78a69027..27c26988 100644 --- a/miasm/arch/arm/jit.py +++ b/miasm/arch/arm/jit.py @@ -33,14 +33,14 @@ class arm_CGen(CGen): if instr.name.startswith("IT"): assignments = [] - label = self.ir_arch.get_instr_label(instr) + label = self.lifter.get_instr_label(instr) irblocks = [] - index, irblocks = self.ir_arch.do_it_block(label, index, block, assignments, True) + index, irblocks = self.lifter.do_it_block(label, index, block, assignments, True) irblocks_list += irblocks continue - assignblk_head, assignblks_extra = self.ir_arch.instr2ir(instr) + assignblk_head, assignblks_extra = self.lifter.instr2ir(instr) # Keep result in ordered list as first element is the assignblk head # The remainings order is not really important irblock_head = self.assignblk_to_irbloc(instr, assignblk_head) diff --git a/miasm/arch/mep/jit.py b/miasm/arch/mep/jit.py index e3cd2428..3fee2537 100644 --- a/miasm/arch/mep/jit.py +++ b/miasm/arch/mep/jit.py @@ -24,10 +24,10 @@ class mep_CGen(CGen): Note: it is used to emulate the *REPEAT instructions """ - def __init__(self, ir_arch): - self.ir_arch = ir_arch - self.PC = self.ir_arch.arch.regs.PC - self.translator = TranslatorC(self.ir_arch.loc_db) + def __init__(self, lifter): + self.lifter = lifter + self.PC = self.lifter.arch.regs.PC + self.translator = TranslatorC(self.lifter.loc_db) self.init_arch_C() def gen_pre_code(self, attrib): @@ -79,7 +79,7 @@ class jitter_mepl(Jitter): def __init__(self, loc_db, *args, **kwargs): Jitter.__init__(self, Lifter_MEPl(loc_db), *args, **kwargs) self.vm.set_little_endian() - self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC + self.lifter.jit_pc = self.lifter.arch.regs.PC def push_uint16_t(self, v): regs = self.cpu.get_gpreg() @@ -109,4 +109,4 @@ class jitter_mepb(jitter_mepl): def __init__(self, loc_db, *args, **kwargs): Jitter.__init__(self, Lifter_MEPb(loc_db), *args, **kwargs) self.vm.set_big_endian() - self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC + self.lifter.jit_pc = self.lifter.arch.regs.PC diff --git a/miasm/arch/mips32/jit.py b/miasm/arch/mips32/jit.py index 779c2b77..53f48303 100644 --- a/miasm/arch/mips32/jit.py +++ b/miasm/arch/mips32/jit.py @@ -34,8 +34,8 @@ class mipsCGen(CGen): return JIT_RET_NO_EXCEPTION; """ - def __init__(self, ir_arch): - super(mipsCGen, self).__init__(ir_arch) + def __init__(self, lifter): + super(mipsCGen, self).__init__(lifter) self.delay_slot_dst = m2_expr.ExprId("branch_dst_irdst", 32) self.delay_slot_set = m2_expr.ExprId("branch_dst_set", 32) @@ -49,17 +49,17 @@ class mipsCGen(CGen): irs = [] for assignblock in irblock: - if self.ir_arch.pc not in assignblock: + if self.lifter.pc not in assignblock: irs.append(AssignBlock(assignments, assignblock.instr)) continue assignments = dict(assignblock) # Add internal branch destination assignments[self.delay_slot_dst] = assignblock[ - self.ir_arch.pc] + self.lifter.pc] assignments[self.delay_slot_set] = m2_expr.ExprInt(1, 32) # Replace IRDst with next instruction - dst_loc_key = self.ir_arch.get_next_instr(assignblock.instr) - assignments[self.ir_arch.IRDst] = m2_expr.ExprLoc(dst_loc_key, 32) + dst_loc_key = self.lifter.get_next_instr(assignblock.instr) + assignments[self.lifter.IRDst] = m2_expr.ExprLoc(dst_loc_key, 32) irs.append(AssignBlock(assignments, assignblock.instr)) irblocks[blk_idx] = IRBlock(irblock.loc_db, irblock.loc_key, irs) @@ -71,7 +71,7 @@ class mipsCGen(CGen): """ loc_key = self.get_block_post_label(block) - offset = self.ir_arch.loc_db.get_location_offset(loc_key) + offset = self.lifter.loc_db.get_location_offset(loc_key) out = (self.CODE_RETURN_NO_EXCEPTION % (loc_key, self.C_PC, m2_expr.ExprId('branch_dst_irdst', 32), diff --git a/miasm/arch/x86/jit.py b/miasm/arch/x86/jit.py index 38301e3c..a90dec07 100644 --- a/miasm/arch/x86/jit.py +++ b/miasm/arch/x86/jit.py @@ -14,10 +14,10 @@ log.setLevel(logging.CRITICAL) class x86_32_CGen(CGen): - def __init__(self, ir_arch): - self.ir_arch = ir_arch - self.PC = self.ir_arch.arch.regs.RIP - self.translator = TranslatorC(self.ir_arch.loc_db) + def __init__(self, lifter): + self.lifter = lifter + self.PC = self.lifter.arch.regs.RIP + self.translator = TranslatorC(self.lifter.loc_db) self.init_arch_C() def gen_post_code(self, attrib, pc_value): @@ -44,20 +44,20 @@ class jitter_x86_16(Jitter): def __init__(self, loc_db, *args, **kwargs): Jitter.__init__(self, Lifter_X86_16(loc_db), *args, **kwargs) self.vm.set_little_endian() - self.ir_arch.do_stk_segm = False - self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode - self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode + self.lifter.do_stk_segm = False + self.orig_irbloc_fix_regs_for_mode = self.lifter.irbloc_fix_regs_for_mode + self.lifter.irbloc_fix_regs_for_mode = self.lifterbloc_fix_regs_for_mode - def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64): + def lifterbloc_fix_regs_for_mode(self, irblock, attrib=64): return self.orig_irbloc_fix_regs_for_mode(irblock, 64) def push_uint16_t(self, value): - self.cpu.SP -= self.ir_arch.sp.size // 8 + self.cpu.SP -= self.lifter.sp.size // 8 self.vm.set_u16(self.cpu.SP, value) def pop_uint16_t(self): value = self.vm.get_u16(self.cpu.SP) - self.cpu.SP += self.ir_arch.sp.size // 8 + self.cpu.SP += self.lifter.sp.size // 8 return value def get_stack_arg(self, index): @@ -75,30 +75,30 @@ class jitter_x86_32(Jitter): def __init__(self, loc_db, *args, **kwargs): Jitter.__init__(self, Lifter_X86_32(loc_db), *args, **kwargs) self.vm.set_little_endian() - self.ir_arch.do_stk_segm = False + self.lifter.do_stk_segm = False - self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode - self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode + self.orig_irbloc_fix_regs_for_mode = self.lifter.irbloc_fix_regs_for_mode + self.lifter.irbloc_fix_regs_for_mode = self.lifterbloc_fix_regs_for_mode - def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64): + def lifterbloc_fix_regs_for_mode(self, irblock, attrib=64): return self.orig_irbloc_fix_regs_for_mode(irblock, 64) def push_uint16_t(self, value): - self.cpu.ESP -= self.ir_arch.sp.size // 8 + self.cpu.ESP -= self.lifter.sp.size // 8 self.vm.set_u16(self.cpu.ESP, value) def pop_uint16_t(self): value = self.vm.get_u16(self.cpu.ESP) - self.cpu.ESP += self.ir_arch.sp.size // 8 + self.cpu.ESP += self.lifter.sp.size // 8 return value def push_uint32_t(self, value): - self.cpu.ESP -= self.ir_arch.sp.size // 8 + self.cpu.ESP -= self.lifter.sp.size // 8 self.vm.set_u32(self.cpu.ESP, value) def pop_uint32_t(self): value = self.vm.get_u32(self.cpu.ESP) - self.cpu.ESP += self.ir_arch.sp.size // 8 + self.cpu.ESP += self.lifter.sp.size // 8 return value def get_stack_arg(self, index): @@ -201,21 +201,21 @@ class jitter_x86_64(Jitter): def __init__(self, loc_db, *args, **kwargs): Jitter.__init__(self, Lifter_X86_64(loc_db), *args, **kwargs) self.vm.set_little_endian() - self.ir_arch.do_stk_segm = False + self.lifter.do_stk_segm = False - self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode - self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode + self.orig_irbloc_fix_regs_for_mode = self.lifter.irbloc_fix_regs_for_mode + self.lifter.irbloc_fix_regs_for_mode = self.lifterbloc_fix_regs_for_mode - def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64): + def lifterbloc_fix_regs_for_mode(self, irblock, attrib=64): return self.orig_irbloc_fix_regs_for_mode(irblock, 64) def push_uint64_t(self, value): - self.cpu.RSP -= self.ir_arch.sp.size // 8 + self.cpu.RSP -= self.lifter.sp.size // 8 self.vm.set_u64(self.cpu.RSP, value) def pop_uint64_t(self): value = self.vm.get_u64(self.cpu.RSP) - self.cpu.RSP += self.ir_arch.sp.size // 8 + self.cpu.RSP += self.lifter.sp.size // 8 return value def get_stack_arg(self, index): |