diff options
Diffstat (limited to 'test')
| -rw-r--r-- | test/analysis/depgraph.py | 4 | ||||
| -rw-r--r-- | test/arch/arm/arch.py | 7 | ||||
| -rwxr-xr-x | test/arch/arm/sem.py | 55 | ||||
| -rw-r--r-- | test/arch/mep/asm/ut_helpers_asm.py | 2 | ||||
| -rw-r--r-- | test/arch/mep/ir/test_loadstore.py | 2 |
5 files changed, 63 insertions, 7 deletions
diff --git a/test/analysis/depgraph.py b/test/analysis/depgraph.py index 57a73a5f..9760e717 100644 --- a/test/analysis/depgraph.py +++ b/test/analysis/depgraph.py @@ -108,7 +108,7 @@ class IRATest(LifterModelCall): def bloc2graph(irgraph, label=False, lines=True): """Render dot graph of @blocks""" - escape_chars = re.compile('[' + re.escape('{}') + ']') + escape_chars = re.compile(r'[\{\}]') label_attr = 'colspan="2" align="center" bgcolor="grey"' edge_attr = 'label = "%s" color="%s" style="bold"' td_attr = 'align="left"' @@ -179,7 +179,7 @@ def bloc2graph(irgraph, label=False, lines=True): def dg2graph(graph, label=False, lines=True): """Render dot graph of @blocks""" - escape_chars = re.compile('[' + re.escape('{}') + ']') + escape_chars = re.compile(r'[\{\}]') label_attr = 'colspan="2" align="center" bgcolor="grey"' edge_attr = 'label = "%s" color="%s" style="bold"' td_attr = 'align="left"' diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py index 42e80772..a3f3a974 100644 --- a/test/arch/arm/arch.py +++ b/test/arch/arm/arch.py @@ -241,7 +241,12 @@ reg_tests_arm = [ '110f111e'), ('XXXXXXXX MCRCC p15, 0x0, R8, c2, c0, 0x1', '308f023e'), - + ('XXXXXXXX MOV R4, R4 ASR 0x20', + '4440a0e1'), + ('XXXXXXXX MOV R2, R5 LSR 0x20', + '2520a0e1'), + ('XXXXXXXX MOVS R2, R5 LSR 0x20', + '2520b0e1'), ] ts = time.time() diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py index a5b6d5eb..343bc063 100755 --- a/test/arch/arm/sem.py +++ b/test/arch/arm/sem.py @@ -81,7 +81,7 @@ class TestARMSemantic(unittest.TestCase): self.assertEqual( compute('MOV R4, R4 LSR 31', {R4: 0xDEADBEEF, }), {R4: 0x00000001, }) self.assertEqual( - compute('MOV R4, R4 LSR 32', {R4: 0xDEADBEEF, }), {R4: 0xDEADBEEF, }) + compute('MOV R4, R4 LSR 32', {R4: 0xDEADBEEF, }), {R4: 0x0, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 LSR 33') self.assertEqual( compute('MOV R4, R4 LSR R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0x6F56DF77, R5: 0xBADBAD01, }) @@ -93,7 +93,7 @@ class TestARMSemantic(unittest.TestCase): self.assertEqual( compute('MOV R4, R4 ASR 31', {R4: 0xDEADBEEF, }), {R4: 0xFFFFFFFF, }) self.assertEqual( - compute('MOV R4, R4 ASR 32', {R4: 0xDEADBEEF, }), {R4: 0xDEADBEEF, }) + compute('MOV R4, R4 ASR 32', {R4: 0xDEADBEEF, }), {R4: 0xFFFFFFFF, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 ASR 33') self.assertEqual( compute('MOV R4, R4 ASR R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0xEF56DF77, R5: 0xBADBAD01, }) @@ -111,6 +111,57 @@ class TestARMSemantic(unittest.TestCase): cf: 0, R4: 0x6F56DF77, }) self.assertEqual(compute('MOV R4, R4 RRX ', {cf: 1, R4: 0xDEADBEEF, }), { cf: 1, R4: 0xEF56DF77, }) + # S + self.assertEqual( + compute('MOVS R4, R4 ', {R4: 0xDEADBEEF, }), {R4: 0xDEADBEEF, nf: 1, zf: 0,}) + self.assertRaises(ValueError, compute, 'MOVS R4, R4 LSL 0') + self.assertEqual( + compute('MOVS R4, R4 LSL 1', {R4: 0xDEADBEEF, }), {R4: 0xBD5B7DDE, nf: 1, zf: 0, cf: 1,}) + self.assertEqual( + compute('MOVS R4, R4 LSL 16', {R4: 0xDEADBEEF, }), {R4: 0xBEEF0000, nf: 1, zf: 0, cf: 1,}) + self.assertEqual( + compute('MOVS R4, R4 LSL 31', {R4: 0xDEADBEEF, }), {R4: 0x80000000, nf: 1, zf: 0, cf: 1,}) + self.assertRaises(ValueError, compute, 'MOVS R4, R4 LSL 32') + self.assertEqual( + compute('MOVS R4, R4 LSL R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0xBD5B7DDE, R5: 0xBADBAD01, nf: 1, zf: 0, cf: 1,}) + self.assertRaises(ValueError, compute, 'MOVS R4, R4 LSR 0') + self.assertEqual( + compute('MOVS R4, R4 LSR 1', {R4: 0xDEADBEEF, }), {R4: 0x6F56DF77, nf: 0, zf: 0, cf: 1,}) + self.assertEqual( + compute('MOVS R4, R4 LSR 16', {R4: 0xDEADBEEF, }), {R4: 0x0000DEAD, nf: 0, zf: 0, cf: 1,}) + self.assertEqual( + compute('MOVS R4, R4 LSR 31', {R4: 0xDEADBEEF, }), {R4: 0x00000001, nf: 0, zf: 0, cf: 1,}) + self.assertEqual( + compute('MOVS R4, R4 LSR 32', {R4: 0xDEADBEEF, }), {R4: 0x0, nf: 0, zf: 1, cf: 1,}) + self.assertRaises(ValueError, compute, 'MOVS R4, R4 LSR 33') + self.assertEqual( + compute('MOVS R4, R4 LSR R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0x6F56DF77, R5: 0xBADBAD01, nf: 0, zf: 0, cf: 1,}) + self.assertRaises(ValueError, compute, 'MOVS R4, R4 ASR 0') + self.assertEqual( + compute('MOVS R4, R4 ASR 1', {R4: 0xDEADBEEF, }), {R4: 0xEF56DF77, nf: 1, zf: 0, cf: 1,}) + self.assertEqual( + compute('MOVS R4, R4 ASR 16', {R4: 0xDEADBEEF, }), {R4: 0xFFFFDEAD, nf: 1, zf: 0, cf: 1,}) + self.assertEqual( + compute('MOVS R4, R4 ASR 31', {R4: 0xDEADBEEF, }), {R4: 0xFFFFFFFF, nf: 1, zf: 0, cf: 1,}) + self.assertEqual( + compute('MOVS R4, R4 ASR 32', {R4: 0xDEADBEEF, }), {R4: 0xFFFFFFFF, nf: 1, zf: 0, cf: 1,}) + self.assertRaises(ValueError, compute, 'MOVS R4, R4 ASR 33') + self.assertEqual( + compute('MOVS R4, R4 ASR R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0xEF56DF77, R5: 0xBADBAD01, nf: 1, zf: 0, cf: 1,}) + self.assertRaises(ValueError, compute, 'MOVS R4, R4 ROR 0') + self.assertEqual( + compute('MOVS R4, R4 ROR 1', {R4: 0xDEADBEEF, }), {R4: 0xEF56DF77, nf: 1, zf: 0, cf: 1,}) + self.assertEqual( + compute('MOVS R4, R4 ROR 16', {R4: 0xDEADBEEF, }), {R4: 0xBEEFDEAD, nf: 1, zf: 0, cf: 1,}) + self.assertEqual( + compute('MOVS R4, R4 ROR 31', {R4: 0xDEADBEEF, }), {R4: 0xBD5B7DDF, nf: 1, zf: 0, cf: 1,}) + self.assertRaises(ValueError, compute, 'MOVS R4, R4 ROR 32') + self.assertEqual( + compute('MOVS R4, R4 ROR R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0xEF56DF77, R5: 0xBADBAD01, nf: 1, zf: 0, cf: 1,}) + self.assertEqual(compute('MOVS R4, R4 RRX ', {cf: 0, R4: 0xDEADBEEF, }), { + cf: 1, R4: 0x6F56DF77, zf: 0, nf: 0}) + self.assertEqual(compute('MOVS R4, R4 RRX ', {cf: 1, R4: 0xDEADBEEF, }), { + cf: 1, R4: 0xEF56DF77, zf: 0, nf: 1}) def test_ADC(self): # §A8.8.1: ADC{S}{<c>}{<q>} {<Rd>,} <Rn>, #<const> diff --git a/test/arch/mep/asm/ut_helpers_asm.py b/test/arch/mep/asm/ut_helpers_asm.py index 9f6dc5c2..2ebd0622 100644 --- a/test/arch/mep/asm/ut_helpers_asm.py +++ b/test/arch/mep/asm/ut_helpers_asm.py @@ -27,7 +27,7 @@ def check_instruction(mn_str, mn_hex, multi=None, offset=0): """Try to disassemble and assemble this instruction""" # Rename objdump registers names - mn_str = re.sub("\$([0-9]+)", lambda m: "R"+m.group(1), mn_str) + mn_str = re.sub(r"\$([0-9]+)", lambda m: "R"+m.group(1), mn_str) mn_str = mn_str.replace("$", "") # Disassemble diff --git a/test/arch/mep/ir/test_loadstore.py b/test/arch/mep/ir/test_loadstore.py index 87343fcb..e7b211bd 100644 --- a/test/arch/mep/ir/test_loadstore.py +++ b/test/arch/mep/ir/test_loadstore.py @@ -83,7 +83,7 @@ class TestLoadStore(object): [(ExprMem(ExprInt(0x1010, 32), 32), ExprInt(0xABC7, 32))]) def test_lb(self): - """Test LB executon""" + """Test LB execution""" # LB Rn,(Rm) exec_instruction("LB R1, (R2)", |