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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-01-21 13:06:54 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-03-09 17:00:47 +0100 |
| commit | 3810e17173c3c1848f44c4fccf0160477a399dab (patch) | |
| tree | f258d5a9623e248efed9eb59c736a0bda1ff2e9e | |
| parent | 71e950afe2b9cc43d1c4186c40c1aa0dced1077d (diff) | |
| download | focaccia-qemu-3810e17173c3c1848f44c4fccf0160477a399dab.tar.gz focaccia-qemu-3810e17173c3c1848f44c4fccf0160477a399dab.zip | |
target/riscv: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250125170125.32855-17-philmd@linaro.org>
Diffstat (limited to '')
| -rw-r--r-- | target/riscv/cpu.c | 8 | ||||
| -rw-r--r-- | target/riscv/internals.h | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1c000c30f8..09ded6829a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1006,9 +1006,9 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) return env->pc; } +#ifndef CONFIG_USER_ONLY bool riscv_cpu_has_work(CPUState *cs) { -#ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; /* @@ -1018,10 +1018,8 @@ bool riscv_cpu_has_work(CPUState *cs) return riscv_cpu_all_pending(env) != 0 || riscv_cpu_sirq_pending(env) != RISCV_EXCP_NONE || riscv_cpu_vsirq_pending(env) != RISCV_EXCP_NONE; -#else - return true; -#endif } +#endif /* !CONFIG_USER_ONLY */ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) { @@ -3029,6 +3027,7 @@ static int64_t riscv_get_arch_id(CPUState *cs) #include "hw/core/sysemu-cpu-ops.h" static const struct SysemuCPUOps riscv_sysemu_ops = { + .has_work = riscv_cpu_has_work, .get_phys_page_debug = riscv_cpu_get_phys_page_debug, .write_elf64_note = riscv_cpu_write_elf64_note, .write_elf32_note = riscv_cpu_write_elf32_note, @@ -3050,7 +3049,6 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = riscv_cpu_class_by_name; - cc->has_work = riscv_cpu_has_work; cc->mmu_index = riscv_cpu_mmu_index; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 67291933f8..213aff31d8 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -142,8 +142,10 @@ static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) } } -/* Our implementation of CPUClass::has_work */ +#ifndef CONFIG_USER_ONLY +/* Our implementation of SysemuCPUOps::has_work */ bool riscv_cpu_has_work(CPUState *cs); +#endif /* Zjpm addr masking routine */ static inline target_ulong adjust_addr_body(CPURISCVState *env, |