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| author | Alexander Graf <agraf@csgraf.de> | 2022-02-09 13:41:35 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-02-21 13:30:19 +0000 |
| commit | 7f6c295cdfeaa229c360cac9a36e4e595aa902ae (patch) | |
| tree | 05f0befb188c3727c9bc94fb71df955f4ebed10b | |
| parent | ad99f64f1cfff7c5e7af0e697523d9b7e45423b6 (diff) | |
| download | focaccia-qemu-7f6c295cdfeaa229c360cac9a36e4e595aa902ae.tar.gz focaccia-qemu-7f6c295cdfeaa229c360cac9a36e4e595aa902ae.zip | |
hvf: arm: Handle unknown ID registers as RES0
Recent Linux versions added support to read ID_AA64ISAR2_EL1. On M1, those reads trap into QEMU which handles them as faults. However, AArch64 ID registers should always read as RES0. Let's handle them accordingly. This fixes booting Linux 5.17 guests. Cc: qemu-stable@nongnu.org Reported-by: Ivan Babrou <ivan@cloudflare.com> Signed-off-by: Alexander Graf <agraf@csgraf.de> Message-id: 20220209124135.69183-2-agraf@csgraf.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to '')
| -rw-r--r-- | target/arm/hvf/hvf.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 808c96da8c..4d4ddab348 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -754,6 +754,15 @@ static bool hvf_handle_psci_call(CPUState *cpu) return true; } +static bool is_id_sysreg(uint32_t reg) +{ + return SYSREG_OP0(reg) == 3 && + SYSREG_OP1(reg) == 0 && + SYSREG_CRN(reg) == 0 && + SYSREG_CRM(reg) >= 1 && + SYSREG_CRM(reg) < 8; +} + static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -806,6 +815,11 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) /* Dummy register */ break; default: + if (is_id_sysreg(reg)) { + /* ID system registers read as RES0 */ + val = 0; + break; + } cpu_synchronize_state(cpu); trace_hvf_unhandled_sysreg_read(env->pc, reg, SYSREG_OP0(reg), |