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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-10-24 14:27:38 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-02-03 23:53:49 +0000 |
| commit | b9ddaf5618adbb9d392ecd6b29b2cb76596de134 (patch) | |
| tree | da1ca9fd86a1638345c92cbd372219c324421611 | |
| parent | 905afe37ab44ff4f55463edba3bb5c6026b815a9 (diff) | |
| download | focaccia-qemu-b9ddaf5618adbb9d392ecd6b29b2cb76596de134.tar.gz focaccia-qemu-b9ddaf5618adbb9d392ecd6b29b2cb76596de134.zip | |
tcg/sparc64: Support TCG_COND_TST{EQ,NE}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to '')
| -rw-r--r-- | tcg/sparc64/tcg-target.c.inc | 16 | ||||
| -rw-r--r-- | tcg/sparc64/tcg-target.h | 2 |
2 files changed, 15 insertions, 3 deletions
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 10fb8a1a0d..176c98740b 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -607,9 +607,11 @@ static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, uns ? ARITH_UDIV : ARITH_SDIV); } -static const uint8_t tcg_cond_to_bcond[] = { +static const uint8_t tcg_cond_to_bcond[16] = { [TCG_COND_EQ] = COND_E, [TCG_COND_NE] = COND_NE, + [TCG_COND_TSTEQ] = COND_E, + [TCG_COND_TSTNE] = COND_NE, [TCG_COND_LT] = COND_L, [TCG_COND_GE] = COND_GE, [TCG_COND_LE] = COND_LE, @@ -649,7 +651,8 @@ static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l) static void tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg c1, int32_t c2, int c2const) { - tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); + tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, + is_tst_cond(cond) ? ARITH_ANDCC : ARITH_SUBCC); } static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, @@ -744,6 +747,15 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); break; + case TCG_COND_TSTEQ: + case TCG_COND_TSTNE: + /* Transform to inequality vs zero. */ + tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_AND); + c1 = TCG_REG_G0; + c2 = TCG_REG_T1, c2const = 0; + cond = (cond == TCG_COND_TSTEQ ? TCG_COND_GEU : TCG_COND_LTU); + break; + case TCG_COND_GTU: case TCG_COND_LEU: /* If we don't need to load a constant into a register, we can diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index ae2910c4ee..a18906a14e 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -149,7 +149,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_qemu_ldst_i128 0 -#define TCG_TARGET_HAS_tst 0 +#define TCG_TARGET_HAS_tst 1 #define TCG_AREG0 TCG_REG_I0 |