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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-01-31 17:03:11 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:46:34 -0800 |
| commit | c9eefe05a42d05d7a6dc49805f123579e5558d5d (patch) | |
| tree | 37279fedf0b69d925880b6eca4dfb7b3abe2c35d | |
| parent | e44b50b5b2e508fdd24915ab0e44ac49685e1de3 (diff) | |
| download | focaccia-qemu-c9eefe05a42d05d7a6dc49805f123579e5558d5d.tar.gz focaccia-qemu-c9eefe05a42d05d7a6dc49805f123579e5558d5d.zip | |
target/riscv: Allow enabling the Hypervisor extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to '')
| -rw-r--r-- | target/riscv/cpu.c | 5 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b27066f6a7..c47d10b739 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -453,6 +453,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_u) { target_misa |= RVU; } + if (cpu->cfg.ext_h) { + target_misa |= RVH; + } set_misa(env, RVXLEN | target_misa); } @@ -488,6 +491,8 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6f9c29322a..d52f209361 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -258,6 +258,7 @@ typedef struct RISCVCPU { bool ext_c; bool ext_s; bool ext_u; + bool ext_h; bool ext_counters; bool ext_ifencei; bool ext_icsr; |