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| author | James Hogan <james.hogan@imgtec.com> | 2016-04-01 15:49:39 +0100 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2016-04-05 12:47:47 -0700 |
| commit | 2dc7553d0c0a3915c649e1a91b0f0be70b4674b3 (patch) | |
| tree | 285c42ff321f2be9255adfa7d34717db3a04ad16 | |
| parent | 43b0ea1a41bd0a02debd48a18e0b5460148e3f40 (diff) | |
| download | focaccia-qemu-2dc7553d0c0a3915c649e1a91b0f0be70b4674b3.tar.gz focaccia-qemu-2dc7553d0c0a3915c649e1a91b0f0be70b4674b3.zip | |
tcg/mips: Fix type of tcg_target_reg_alloc_order[]
The MIPS TCG backend is the only one to have
tcg_target_reg_alloc_order[] elements of type TCGReg rather than int.
This resulted in commit 91478cefaaf2 ("tcg: Allocate indirect_base
temporaries in a different order") breaking the build on MIPS since the
type differed from indirect_reg_alloc_order[]:
tcg/tcg.c:1725:44: error: pointer type mismatch in conditional expression [-Werror]
order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order;
^
Make it an array of ints to fix the build and match other architectures.
Fixes: 91478cefaaf2 ("tcg: Allocate indirect_base temporaries in a different order")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Message-Id: <1459522179-6584-1-git-send-email-james.hogan@imgtec.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to '')
| -rw-r--r-- | tcg/mips/tcg-target.inc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 297bd00910..682e19897d 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -76,7 +76,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #define TCG_TMP1 TCG_REG_T9 /* check if we really need so many registers :P */ -static const TCGReg tcg_target_reg_alloc_order[] = { +static const int tcg_target_reg_alloc_order[] = { /* Call saved registers. */ TCG_REG_S0, TCG_REG_S1, |