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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-10-06 16:46:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-10-06 16:46:48 +0100 |
| commit | 4e4259d3c574a8e89c3af27bcb84bc19a442efb1 (patch) | |
| tree | d5fec04a8ac238c51e22872a8c0dcbcc055a1587 | |
| parent | cb484f9a6e790205e69d9a444c3e353a3a1cfd84 (diff) | |
| download | focaccia-qemu-4e4259d3c574a8e89c3af27bcb84bc19a442efb1.tar.gz focaccia-qemu-4e4259d3c574a8e89c3af27bcb84bc19a442efb1.zip | |
target/arm: Don't warn about exception return with PC low bit set for v8M
In the v8M architecture, return from an exception to a PC which has bit 0 set is not UNPREDICTABLE; it is defined that bit 0 is discarded [R_HRJH]. Restrict our complaint about this to v7M. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-9-git-send-email-peter.maydell@linaro.org
Diffstat (limited to '')
| -rw-r--r-- | target/arm/helper.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index bb57be73bf..c7cf24ccb9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6431,16 +6431,24 @@ static void do_v7m_exception_exit(ARMCPU *cpu) env->regs[12] = ldl_phys(cs->as, frameptr + 0x10); env->regs[14] = ldl_phys(cs->as, frameptr + 0x14); env->regs[15] = ldl_phys(cs->as, frameptr + 0x18); + + /* Returning from an exception with a PC with bit 0 set is defined + * behaviour on v8M (bit 0 is ignored), but for v7M it was specified + * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore + * the lsbit, and there are several RTOSes out there which incorrectly + * assume the r15 in the stack frame should be a Thumb-style "lsbit + * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but + * complain about the badly behaved guest. + */ if (env->regs[15] & 1) { - qemu_log_mask(LOG_GUEST_ERROR, - "M profile return from interrupt with misaligned " - "PC is UNPREDICTABLE\n"); - /* Actual hardware seems to ignore the lsbit, and there are several - * RTOSes out there which incorrectly assume the r15 in the stack - * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value. - */ env->regs[15] &= ~1U; + if (!arm_feature(env, ARM_FEATURE_V8)) { + qemu_log_mask(LOG_GUEST_ERROR, + "M profile return from interrupt with misaligned " + "PC is UNPREDICTABLE on v7M\n"); + } } + xpsr = ldl_phys(cs->as, frameptr + 0x1c); if (arm_feature(env, ARM_FEATURE_V8)) { |