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| author | Bin Meng <bmeng@tinylab.org> | 2023-01-09 23:26:55 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-01-20 10:14:13 +1000 |
| commit | 877a3a3732dcd45b09b96a6ff9655f6a2e19540f (patch) | |
| tree | 94cf75ea23c65b9b735edfb7a97df92666a3fe0c | |
| parent | 5ab1095213318effd9bb4667f7f52da21f81acc6 (diff) | |
| download | focaccia-qemu-877a3a3732dcd45b09b96a6ff9655f6a2e19540f.tar.gz focaccia-qemu-877a3a3732dcd45b09b96a6ff9655f6a2e19540f.zip | |
target/riscv: Use TARGET_FMT_lx for env->mhartid
env->mhartid is currently casted to long before printed, which drops the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230109152655.340114-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to '')
| -rw-r--r-- | target/riscv/cpu.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c192d96a94..14a7027095 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -867,9 +867,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) (env->priv_ver < isa_edata_arr[i].min_version)) { isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); #ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x%lx because " - "privilege spec version does not match", - isa_edata_arr[i].name, (unsigned long)env->mhartid); + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + isa_edata_arr[i].name, env->mhartid); #else warn_report("disabling %s extension because " "privilege spec version does not match", |