summary refs log tree commit diff stats
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2017-10-09 14:48:31 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-10-12 13:23:14 +0100
commitb9f587d62cebed427206539750ebf59bde4df422 (patch)
tree814d04577f6b6f871aee0c6f642080c0472b5083
parent8602beb7fad4b2abd5341f4303ec3c799fa0217c (diff)
downloadfocaccia-qemu-b9f587d62cebed427206539750ebf59bde4df422.tar.gz
focaccia-qemu-b9f587d62cebed427206539750ebf59bde4df422.zip
target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()
Add the M profile secure MMU index values to the switch in
get_a32_user_mem_index() so that LDRT/STRT work correctly
rather than asserting at translate time.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-2-git-send-email-peter.maydell@linaro.org
Diffstat (limited to '')
-rw-r--r--target/arm/translate.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c
index fdc46cc525..61fd0ef6b5 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -165,6 +165,10 @@ static inline int get_a32_user_mem_index(DisasContext *s)
     case ARMMMUIdx_MPriv:
     case ARMMMUIdx_MNegPri:
         return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
+    case ARMMMUIdx_MSUser:
+    case ARMMMUIdx_MSPriv:
+    case ARMMMUIdx_MSNegPri:
+        return arm_to_core_mmu_idx(ARMMMUIdx_MSUser);
     case ARMMMUIdx_S2NS:
     default:
         g_assert_not_reached();