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authorIrina Ryapolova <irina.ryapolova@syntacore.com>2024-03-20 20:28:28 +0300
committerAlistair Francis <alistair.francis@wdc.com>2024-03-22 15:32:33 +1000
commite06adebb08325c39e4c9b652139426c10f021abb (patch)
tree181eeae62475a7cf66fb493b0296d448f5963ace
parentc9b07fe14d3525cd3f2fc01f46eeb3d4ed7c3603 (diff)
downloadfocaccia-qemu-e06adebb08325c39e4c9b652139426c10f021abb.tar.gz
focaccia-qemu-e06adebb08325c39e4c9b652139426c10f021abb.zip
target/riscv: Fix mode in riscv_tlb_fill
Need to convert mmu_idx to privilege mode for PMP function.

Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
Fixes: b297129ae1 ("target/riscv: propagate PMP permission to TLB page")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240320172828.23965-1-irina.ryapolova@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to '')
-rw-r--r--target/riscv/cpu_helper.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ce7322011d..fc090d729a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1315,7 +1315,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     bool two_stage_lookup = mmuidx_2stage(mmu_idx);
     bool two_stage_indirect_error = false;
     int ret = TRANSLATE_FAIL;
-    int mode = mmu_idx;
+    int mode = mmuidx_priv(mmu_idx);
     /* default TLB page size */
     target_ulong tlb_size = TARGET_PAGE_SIZE;