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| author | Bin Meng <bin.meng@windriver.com> | 2020-06-15 17:50:37 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-19 08:25:27 -0700 |
| commit | e8905c6ce86f5023f6814abd7c72a809e5d018ec (patch) | |
| tree | 9aa2ac588d640b5c41867877563c15c6e9ea25f7 | |
| parent | cfa32630d914373413c0b42faf756ccaabc4bbb9 (diff) | |
| download | focaccia-qemu-e8905c6ce86f5023f6814abd7c72a809e5d018ec.tar.gz focaccia-qemu-e8905c6ce86f5023f6814abd7c72a809e5d018ec.zip | |
target/riscv: Rename IBEX CPU init routine
Current IBEX CPU init routine name seems to be too generic. Since it uses a different reset vector from the generic one, it merits a dedicated name. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-2-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to '')
| -rw-r--r-- | target/riscv/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e867766cf0..5f034588ec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,7 +153,7 @@ static void rvxx_imacu_nommu_cpu_init(Object *obj) #if defined(TARGET_RISCV32) -static void rv32_imcu_nommu_cpu_init(Object *obj) +static void rv32_ibex_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RV32 | RVI | RVM | RVC | RVU); @@ -577,7 +577,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_imcu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_gcsu_priv1_10_0_cpu_init), |