diff options
| author | Max Chou <max.chou@sifive.com> | 2025-04-08 18:39:33 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-05-19 13:38:56 +1000 |
| commit | fda68acb7761af40df78db18e44ca1ff20195fe0 (patch) | |
| tree | f4b84140b62fee7c0d548ac8845e1f79474018ad | |
| parent | fbeaf35838768086b435833cb4dc5182c73ec2bc (diff) | |
| download | focaccia-qemu-fda68acb7761af40df78db18e44ca1ff20195fe0.tar.gz focaccia-qemu-fda68acb7761af40df78db18e44ca1ff20195fe0.zip | |
target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions
Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard <antonb@tenstorrent.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20250408103938.3623486-6-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Cc: qemu-stable@nongnu.org
Diffstat (limited to '')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index b1e1db04a0..5de50422c9 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -432,6 +432,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm) static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm) { return vext_check_ss(s, vd, vs2, vm) && + vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) && require_align(vs1, s->lmul); } |