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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-24 14:22:25 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-28 16:14:57 +0000 |
| commit | 46c98019255b056f5dbc9676a6490951469ca661 (patch) | |
| tree | 8eeea3be49c6f56fdea012268dc593a411a7bad8 | |
| parent | c52881bbc22b50db99a6c37171ad3eea7d959ae6 (diff) | |
| download | focaccia-qemu-46c98019255b056f5dbc9676a6490951469ca661.tar.gz focaccia-qemu-46c98019255b056f5dbc9676a6490951469ca661.zip | |
target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn
We now have proper ISA checks within each trans_* function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/translate.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 0489e0cdaa..893911fca7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2652,10 +2652,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) */ static int disas_vfp_insn(DisasContext *s, uint32_t insn) { - if (!arm_dc_feature(s, ARM_FEATURE_VFP)) { - return 1; - } - /* * If the decodetree decoder handles this insn it will always * emit code to either execute the insn or generate an appropriate |