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| author | Jim Shu <cwshu@andestech.com> | 2021-02-21 22:01:21 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-03-22 21:54:40 -0400 |
| commit | 663e119317d77780949830226f5575305405ab75 (patch) | |
| tree | 4f971b83b3919444f046448a906a3ebbacc0e296 | |
| parent | b297129ae19e26d3cc0e376d2bfc33d76b06d83b (diff) | |
| download | focaccia-qemu-663e119317d77780949830226f5575305405ab75.tar.gz focaccia-qemu-663e119317d77780949830226f5575305405ab75.zip | |
target/riscv: add log of PMP permission checking
Like MMU translation, add qemu log of PMP permission checking for debugging. Signed-off-by: Jim Shu <cwshu@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu_helper.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fa385594df..0515f9aec8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -794,6 +794,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (ret == TRANSLATE_SUCCESS) { ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, size, access_type, mode); + + qemu_log_mask(CPU_LOG_MMU, + "%s PMP address=" TARGET_FMT_plx " ret %d prot" + " %d tlb_size " TARGET_FMT_lu "\n", + __func__, pa, ret, prot_pmp, tlb_size); + prot &= prot_pmp; } @@ -821,6 +827,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (ret == TRANSLATE_SUCCESS) { ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, size, access_type, mode); + + qemu_log_mask(CPU_LOG_MMU, + "%s PMP address=" TARGET_FMT_plx " ret %d prot" + " %d tlb_size " TARGET_FMT_lu "\n", + __func__, pa, ret, prot_pmp, tlb_size); + prot &= prot_pmp; } } |