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authorRob Bradford <rbradford@rivosinc.com>2025-02-06 15:34:10 +0000
committerAlistair Francis <alistair.francis@wdc.com>2025-03-04 15:42:54 +1000
commit81819038d7d01c6c8c12005b5904356efc09a909 (patch)
tree4f60e1255a9e7cf65f1bc7110f118d4f05d187c4
parentd30db4df5187e2b91e589ffceace59a0ae2bc30e (diff)
downloadfocaccia-qemu-81819038d7d01c6c8c12005b5904356efc09a909.tar.gz
focaccia-qemu-81819038d7d01c6c8c12005b5904356efc09a909.zip
disas/riscv: Add missing Sdtrig CSRs
This reflects the latest frozen version of the RISC-V Debug
specification (1.0.0-rc4) which includes the Sdtrig extension.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250206153410.236636-3-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r--disas/riscv.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/disas/riscv.c b/disas/riscv.c
index 305dd40ac4..85cd2a9c2a 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2438,9 +2438,11 @@ static const char *csr_name(int csrno)
     case 0x07a1: return "tdata1";
     case 0x07a2: return "tdata2";
     case 0x07a3: return "tdata3";
+    case 0x07a4: return "tinfo";
     case 0x07b0: return "dcsr";
     case 0x07b1: return "dpc";
-    case 0x07b2: return "dscratch";
+    case 0x07b2: return "dscratch0";
+    case 0x07b3: return "dscratch1";
     case 0x0b00: return "mcycle";
     case 0x0b01: return "mtime";
     case 0x0b02: return "minstret";