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authorRichard Henderson <richard.henderson@linaro.org>2019-08-25 17:33:53 -0700
committerRichard Henderson <richard.henderson@linaro.org>2019-09-04 13:01:56 -0700
commit9e3bab08d3e3f5808cc35a59af1912bfb6fe96fd (patch)
tree3a79d3ae876bc02eea9bd1dbb4e4029fbd4b10d8
parent3e0e41ef33a841bdefaaf2fd9224fd791da9d2c6 (diff)
downloadfocaccia-qemu-9e3bab08d3e3f5808cc35a59af1912bfb6fe96fd.tar.gz
focaccia-qemu-9e3bab08d3e3f5808cc35a59af1912bfb6fe96fd.zip
target/openrisc: Update cpu "any" to v1.3
Now that the two updates from v1.3 are implemented,
update the "any" cpu to enable it.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--target/openrisc/cpu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index f96a69e278..506aec6bfb 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -129,7 +129,7 @@ static void openrisc_any_initfn(Object *obj)
 
     cpu->env.vr = 0x13000040;   /* Obsolete VER + UVRP for new SPRs */
     cpu->env.vr2 = 0;           /* No version specific id */
-    cpu->env.avr = 0x01010000;  /* Architecture v1.1 */
+    cpu->env.avr = 0x01030000;  /* Architecture v1.3 */
 
     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |