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| author | Peter Crosthwaite <crosthwaitepeter@gmail.com> | 2015-07-11 19:00:01 -0700 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2015-10-22 15:49:40 +0200 |
| commit | df0900eb89a0672a3f924b7e8d20163dee2383db (patch) | |
| tree | 31462c643042032eccef68446a6d677b14f0eb5b | |
| parent | 4f669905d95bbb6296338f9e86ffcdd8eae453d2 (diff) | |
| download | focaccia-qemu-df0900eb89a0672a3f924b7e8d20163dee2383db.tar.gz focaccia-qemu-df0900eb89a0672a3f924b7e8d20163dee2383db.zip | |
disas: QOMify sparc specific disas setup
Move the target_disas() sparc specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c. Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
| -rw-r--r-- | disas.c | 10 | ||||
| -rw-r--r-- | target-sparc/cpu.c | 9 |
2 files changed, 9 insertions, 10 deletions
diff --git a/disas.c b/disas.c index 1ef259632e..5b3acf0324 100644 --- a/disas.c +++ b/disas.c @@ -214,11 +214,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code, s.info.mach = bfd_mach_i386_i386; } s.info.print_insn = print_insn_i386; -#elif defined(TARGET_SPARC) - s.info.print_insn = print_insn_sparc; -#ifdef TARGET_SPARC64 - s.info.mach = bfd_mach_sparc_v9b; -#endif #elif defined(TARGET_PPC) if ((flags >> 16) & 1) { s.info.endian = BFD_ENDIAN_LITTLE; @@ -423,11 +418,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu, s.info.print_insn = print_insn_i386; #elif defined(TARGET_ALPHA) s.info.print_insn = print_insn_alpha; -#elif defined(TARGET_SPARC) - s.info.print_insn = print_insn_sparc; -#ifdef TARGET_SPARC64 - s.info.mach = bfd_mach_sparc_v9b; -#endif #elif defined(TARGET_PPC) if (flags & 0xFFFF) { /* If we have a precise definition of the instruction set, use it. */ diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 82bb72ab79..d98682b563 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -90,6 +90,14 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + info->print_insn = print_insn_sparc; +#ifdef TARGET_SPARC64 + info->mach = bfd_mach_sparc_v9b; +#endif +} + static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model) { CPUClass *cc = CPU_GET_CLASS(cpu); @@ -848,6 +856,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->do_unaligned_access = sparc_cpu_do_unaligned_access; cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; #endif + cc->disas_set_info = cpu_sparc_disas_set_info; #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) cc->gdb_num_core_regs = 86; |