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| author | Tao Su <tao1.su@linux.intel.com> | 2024-10-31 16:52:32 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-10-31 18:28:33 +0100 |
| commit | 0d7475be3b402c25d74c5a4573cbeb733c8f3559 (patch) | |
| tree | daeb0fca208753003075d7d2cb61adfd42f526a5 | |
| parent | 150ab84b2d0083e6af344cca70290614d4fe568d (diff) | |
| download | focaccia-qemu-0d7475be3b402c25d74c5a4573cbeb733c8f3559.tar.gz focaccia-qemu-0d7475be3b402c25d74c5a4573cbeb733c8f3559.zip | |
target/i386: Add AVX512 state when AVX10 is supported
AVX10 state enumeration in CPUID leaf D and enabling in XCR0 register are identical to AVX512 state regardless of the supported vector lengths. Given that some E-cores will support AVX10 but not support AVX512, add AVX512 state components to guest when AVX10 is enabled. Based on a patch by Tao Su <tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Tested-by: Xuelian Guo <xuelian.guo@intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Link: https://lore.kernel.org/r/20241031085233.425388-8-tao1.su@linux.intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d056285a03..7666a50bf0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7156,7 +7156,15 @@ static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) return false; } - return (env->features[esa->feature] & esa->bits); + if (env->features[esa->feature] & esa->bits) { + return true; + } + if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F + && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { + return true; + } + + return false; } static void x86_cpu_reset_hold(Object *obj, ResetType type) |