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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-12-19 17:57:49 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-12-19 17:57:49 +0000 |
| commit | 7a3014a9a26b61b1df246426b6510b8956acfaab (patch) | |
| tree | af9337cf07e59ba2129af27e927b4e7cb5a4adeb | |
| parent | d1d119bbd7776c8f460560e4f4b69fdc8bfd8657 (diff) | |
| download | focaccia-qemu-7a3014a9a26b61b1df246426b6510b8956acfaab.tar.gz focaccia-qemu-7a3014a9a26b61b1df246426b6510b8956acfaab.zip | |
target/arm: Restrict DC CVAP & DC CVADP instructions to TCG accel
Hardware accelerators handle that in *hardware*. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231130142519.28417-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 5d4796b99a..436a43a4b7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7649,6 +7649,7 @@ static const ARMCPRegInfo rndr_reginfo[] = { static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, uint64_t value) { +#ifdef CONFIG_TCG ARMCPU *cpu = env_archcpu(env); /* CTR_EL0 System register -> DminLine, bits [19:16] */ uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); @@ -7673,6 +7674,10 @@ static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, } #endif /*CONFIG_USER_ONLY*/ } +#else + /* Handled by hardware accelerator. */ + g_assert_not_reached(); +#endif /* CONFIG_TCG */ } static const ARMCPRegInfo dcpop_reg[] = { |