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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2016-03-04 11:30:20 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-03-04 11:30:20 +0000 |
| commit | 91cca2cda9823b1e7a049cb308a05104b5076cba (patch) | |
| tree | 704bd5ac2ea83856a3b59dd15ea97b3857c66a8d | |
| parent | aa6489da4e297fb3ffcbc09b50afd700395b6386 (diff) | |
| download | focaccia-qemu-91cca2cda9823b1e7a049cb308a05104b5076cba.tar.gz focaccia-qemu-91cca2cda9823b1e7a049cb308a05104b5076cba.zip | |
target-arm: introduce tbflag for endianness
Introduce a tbflags for endianness, set based upon the CPUs current endianness. This in turn propagates through to the disas endianness flag. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-arm/cpu.h | 7 | ||||
| -rw-r--r-- | target-arm/translate-a64.c | 2 | ||||
| -rw-r--r-- | target-arm/translate.c | 2 |
3 files changed, 9 insertions, 2 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cbf171cc23..279c91fefd 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1985,6 +1985,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) */ #define ARM_TBFLAG_NS_SHIFT 19 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) +#define ARM_TBFLAG_BE_DATA_SHIFT 20 +#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) /* Bit usage when in AArch64 state: currently we have no A64 specific bits */ @@ -2015,6 +2017,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) #define ARM_TBFLAG_NS(F) \ (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) +#define ARM_TBFLAG_BE_DATA(F) \ + (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) static inline bool bswap_code(bool sctlr_b) { @@ -2157,6 +2161,9 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } } + if (arm_cpu_data_is_big_endian(env)) { + *flags |= ARM_TBFLAG_BE_DATA_MASK; + } *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; *cs_base = 0; diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 539e6d9c69..f0c73df5b0 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11043,7 +11043,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) !arm_el_is_aa64(env, 3); dc->thumb = 0; dc->sctlr_b = 0; - dc->be_data = MO_TE; + dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; dc->condexec_mask = 0; dc->condexec_cond = 0; dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags); diff --git a/target-arm/translate.c b/target-arm/translate.c index 2d4b1ccf1d..c430fec7ad 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11330,7 +11330,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) !arm_el_is_aa64(env, 3); dc->thumb = ARM_TBFLAG_THUMB(tb->flags); dc->sctlr_b = ARM_TBFLAG_SCTLR_B(tb->flags); - dc->be_data = MO_TE; + dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags); |