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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-08-27 20:38:40 +1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-09-04 09:49:23 +0200 |
| commit | ba8a86d67aca43a854c78380c917845059c83d4c (patch) | |
| tree | 643464e058e4635bae9a90f049a1f0c3f2a7b013 | |
| parent | 26c41cc4a3d998caa700407a27e18755a6e1895c (diff) | |
| download | focaccia-qemu-ba8a86d67aca43a854c78380c917845059c83d4c.tar.gz focaccia-qemu-ba8a86d67aca43a854c78380c917845059c83d4c.zip | |
tcg/i386: Use canonical operand ordering in expand_vec_sari
The optimizer prefers to have constants as the second operand, so expand LT x,0 instead of GT 0,x. This will not affect the generated code at all. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/i386/tcg-target.c.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 4cd5d4276c..8260c35edd 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -4399,8 +4399,8 @@ static void expand_vec_sari(TCGType type, unsigned vece, /* Otherwise we will need to use a compare vs 0 to produce * the sign-extend, shift and merge. */ - tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, - tcg_constant_vec(type, MO_64, 0), v1); + tcg_gen_cmp_vec(TCG_COND_LT, MO_64, t1, v1, + tcg_constant_vec(type, MO_64, 0)); tcg_gen_shri_vec(MO_64, v0, v1, imm); tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm); tcg_gen_or_vec(MO_64, v0, v0, t1); |