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| author | Yoshinori Sato <ysato@users.sourceforge.jp> | 2022-02-07 22:27:58 +0900 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-04-21 10:06:42 -0700 |
| commit | bcc6f33b671d223a1d7b81491d45c58b35ed6e3e (patch) | |
| tree | 13a1ea45e1cd43161db82ad4ade68ed66ef144ad | |
| parent | 3c69336a8773ec9dde145d40f3e715b9395e0aa0 (diff) | |
| download | focaccia-qemu-bcc6f33b671d223a1d7b81491d45c58b35ed6e3e.tar.gz focaccia-qemu-bcc6f33b671d223a1d7b81491d45c58b35ed6e3e.zip | |
hw/rx: rx-gdbsim DTB load address aligned of 16byte.
Linux kernel required alined address of DTB. But missing align in dtb load function. Fixed to load to the correct address. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220207132758.84403-1-ysato@users.sourceforge.jp> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | hw/rx/rx-gdbsim.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c index 64f897e5b1..be147b4bd9 100644 --- a/hw/rx/rx-gdbsim.c +++ b/hw/rx/rx-gdbsim.c @@ -141,7 +141,7 @@ static void rx_gdbsim_init(MachineState *machine) exit(1); } /* DTB is located at the end of SDRAM space. */ - dtb_offset = machine->ram_size - dtb_size; + dtb_offset = ROUND_DOWN(machine->ram_size - dtb_size, 16); rom_add_blob_fixed("dtb", dtb, dtb_size, SDRAM_BASE + dtb_offset); /* Set dtb address to R1 */ |