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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2024-11-14 17:48:39 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-01-27 09:38:15 +0100 |
| commit | bf8a471a38774800d77f58949bcaea4ca26390a7 (patch) | |
| tree | af7c328cc4000bb8e5f05c08d7478d5f3fc81c32 | |
| parent | 134d9e5c0c4ae2fe64817a185730ec8b7835d573 (diff) | |
| download | focaccia-qemu-bf8a471a38774800d77f58949bcaea4ca26390a7.tar.gz focaccia-qemu-bf8a471a38774800d77f58949bcaea4ca26390a7.zip | |
hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2600 EVB, the Write Protected pin is active high by default. To support it, introduces a new "sdhci_wp_inverted" property in ASPEED MACHINE State and set it true for AST2600 EVB and set "wp_inverted" property true of sdhci-generic model. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20241114094839.4128404-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| -rw-r--r-- | hw/arm/aspeed.c | 7 | ||||
| -rw-r--r-- | include/hw/arm/aspeed.h | 1 |
2 files changed, 8 insertions, 0 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 2662465ada..53a859a6e4 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -409,6 +409,12 @@ static void aspeed_machine_init(MachineState *machine) OBJECT(get_system_memory()), &error_abort); object_property_set_link(OBJECT(bmc->soc), "dram", OBJECT(machine->ram), &error_abort); + if (amc->sdhci_wp_inverted) { + for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { + object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), + "wp-inverted", true, &error_abort); + } + } if (machine->kernel_filename) { /* * When booting with a -kernel command line there is no u-boot @@ -1415,6 +1421,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) amc->num_cs = 1; amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; + amc->sdhci_wp_inverted = true; amc->i2c_init = ast2600_evb_i2c_init; mc->default_ram_size = 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index cbeacb214c..9cae45a1c9 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -39,6 +39,7 @@ struct AspeedMachineClass { uint32_t macs_mask; void (*i2c_init)(AspeedMachineState *bmc); uint32_t uart_default; + bool sdhci_wp_inverted; }; |