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authorRichard Henderson <richard.henderson@linaro.org>2023-08-31 09:45:15 +0100
committerPeter Maydell <peter.maydell@linaro.org>2023-08-31 09:45:15 +0100
commitcd305b5f311d6ecea6cf487f3ec78b84bcd60d63 (patch)
tree304c3cdd2b1d5513b708ea17020c5c333bf821b1
parent7134cb07b749b669c25526c044b19204686f4663 (diff)
downloadfocaccia-qemu-cd305b5f311d6ecea6cf487f3ec78b84bcd60d63.tar.gz
focaccia-qemu-cd305b5f311d6ecea6cf487f3ec78b84bcd60d63.zip
target/arm: When tag memory is not present, set MTE=1
When the cpu support MTE, but the system does not, reduce cpu
support to user instructions at EL0 instead of completely
disabling MTE.  If we encounter a cpu implementation which does
something else, we can revisit this setting.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/cpu.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index fe73fd8af7..23901121ac 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2067,12 +2067,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 
 #ifndef CONFIG_USER_ONLY
         /*
-         * Disable the MTE feature bits if we do not have tag-memory
-         * provided by the machine.
+         * If we do not have tag-memory provided by the machine,
+         * reduce MTE support to instructions enabled at EL0.
+         * This matches Cortex-A710 BROADCASTMTE input being LOW.
          */
         if (cpu->tag_memory == NULL) {
             cpu->isar.id_aa64pfr1 =
-                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
         }
 #endif
     }