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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2022-03-05 15:09:46 +0000 |
|---|---|---|
| committer | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2022-03-09 09:28:28 +0000 |
| commit | d05bacbf7607937954f2e07c68d4c1ffb10abc16 (patch) | |
| tree | be1f7e2d14bd8aa63757c75af99edf42701fe542 | |
| parent | 9f0369efb0f2a200f18b1aacd2ef493e22da5351 (diff) | |
| download | focaccia-qemu-d05bacbf7607937954f2e07c68d4c1ffb10abc16.tar.gz focaccia-qemu-d05bacbf7607937954f2e07c68d4c1ffb10abc16.zip | |
mos6522: add defines for IFR bit flags
These are intended to make it easier to see how the physical control lines are wired for each instance. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220305150957.5053-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
| -rw-r--r-- | include/hw/misc/mos6522.h | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index fc95d22b0f..be5c90d24d 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -41,13 +41,21 @@ #define IER_SET 0x80 /* set bits in IER */ #define IER_CLR 0 /* clear bits in IER */ -#define CA2_INT 0x01 -#define CA1_INT 0x02 -#define SR_INT 0x04 /* Shift register full/empty */ -#define CB2_INT 0x08 -#define CB1_INT 0x10 -#define T2_INT 0x20 /* Timer 2 interrupt */ -#define T1_INT 0x40 /* Timer 1 interrupt */ +#define CA2_INT_BIT 0 +#define CA1_INT_BIT 1 +#define SR_INT_BIT 2 /* Shift register full/empty */ +#define CB2_INT_BIT 3 +#define CB1_INT_BIT 4 +#define T2_INT_BIT 5 /* Timer 2 interrupt */ +#define T1_INT_BIT 6 /* Timer 1 interrupt */ + +#define CA2_INT BIT(CA2_INT_BIT) +#define CA1_INT BIT(CA1_INT_BIT) +#define SR_INT BIT(SR_INT_BIT) +#define CB2_INT BIT(CB2_INT_BIT) +#define CB1_INT BIT(CB1_INT_BIT) +#define T2_INT BIT(T2_INT_BIT) +#define T1_INT BIT(T1_INT_BIT) /* Bits in ACR */ #define T1MODE 0xc0 /* Timer 1 mode */ |