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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-02-11 17:04:57 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-11 17:04:57 +0000 |
| commit | 22c5f446514a2a4bb0dbe1fea26713da92fc85fa (patch) | |
| tree | a2b37a81e8ae1f0764ecdafef2c652a889e5d628 /accel/tcg/cputlb.c | |
| parent | a044e3de2917d54b95f1211f4d14ec30cac9a59f (diff) | |
| parent | 6d967cb86d5b4a60ba15b497126b621ce9ca6609 (diff) | |
| download | focaccia-qemu-22c5f446514a2a4bb0dbe1fea26713da92fc85fa.tar.gz focaccia-qemu-22c5f446514a2a4bb0dbe1fea26713da92fc85fa.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190211' into staging
Fix dynamic tlb resize Fix x86 host vector saturation Diagnose missing tcg labels # gpg: Signature made Mon 11 Feb 2019 16:57:52 GMT # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190211: cputlb: update TLB entry/index after tlb_fill exec-all: document that tlb_fill can trigger a TLB resize tcg/i386: fix unsigned vector saturating arithmetic tcg: Diagnose referenced labels that have not been emitted Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'accel/tcg/cputlb.c')
| -rw-r--r-- | accel/tcg/cputlb.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f580e4dd7e..88cc8389e9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1045,6 +1045,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) if (unlikely(!tlb_hit(entry->addr_code, addr))) { if (!VICTIM_TLB_HIT(addr_code, addr)) { tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0); + index = tlb_index(env, mmu_idx, addr); + entry = tlb_entry(env, mmu_idx, addr); } assert(tlb_hit(entry->addr_code, addr)); } @@ -1125,6 +1127,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE, mmu_idx, retaddr); + index = tlb_index(env, mmu_idx, addr); + tlbe = tlb_entry(env, mmu_idx, addr); } tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; } |