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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-08-15 15:00:57 -0500 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-10-04 12:13:04 -0700 |
| commit | 93b996161b54860ded173f54ed96257717bb9728 (patch) | |
| tree | d4557fe8738dd29451cd39c5b2c1de25c9e46d2d /accel/tcg/cputlb.c | |
| parent | b21af662c15522b83a973bc2ffd51d0117c0e039 (diff) | |
| download | focaccia-qemu-93b996161b54860ded173f54ed96257717bb9728.tar.gz focaccia-qemu-93b996161b54860ded173f54ed96257717bb9728.zip | |
accel/tcg: Do not align tb->page_addr[0]
Let tb->page_addr[0] contain the address of the first byte of the translated block, rather than the address of the page containing the start of the translated block. We need to recover this value anyway at various points, and it is easier to discard a page offset when it is not needed, which happens naturally via the existing find_page shift. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'accel/tcg/cputlb.c')
| -rw-r--r-- | accel/tcg/cputlb.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 361078471b..a0db2d32a8 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -951,7 +951,8 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, can be detected */ void tlb_protect_code(ram_addr_t ram_addr) { - cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE, + cpu_physical_memory_test_and_clear_dirty(ram_addr & TARGET_PAGE_MASK, + TARGET_PAGE_SIZE, DIRTY_MEMORY_CODE); } |