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| author | Anthony Liguori <aliguori@us.ibm.com> | 2012-03-14 16:47:49 -0500 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2012-03-14 16:47:49 -0500 |
| commit | aea6ff7fa07b046fb9f43d6262d6e34b77e8437e (patch) | |
| tree | dd3043d1742273a95fa7fc5e99b8d5ffe0c710e5 /arm-semi.c | |
| parent | 9e4dd565b46749d5e6d5cf87bfd84f1917c68319 (diff) | |
| parent | dd83b06ae61cfa2dc4381ab49f365bd0995fc930 (diff) | |
| download | focaccia-qemu-aea6ff7fa07b046fb9f43d6262d6e34b77e8437e.tar.gz focaccia-qemu-aea6ff7fa07b046fb9f43d6262d6e34b77e8437e.zip | |
Merge remote-tracking branch 'afaerber/qom-cpu.v5' into staging
* afaerber/qom-cpu.v5: (43 commits) qom: Introduce CPU class Rename CPUState -> CPUArchState xtensa hw/: Don't use CPUState sparc hw/: Don't use CPUState sh4 hw/: Don't use CPUState s390x hw/: Don't use CPUState ppc hw/: Don't use CPUState mips hw/: Don't use CPUState microblaze hw/: Don't use CPUState m68k hw/: Don't use CPUState lm32 hw/: Don't use CPUState i386 hw/: Don't use CPUState cris hw/: Don't use CPUState arm hw/: Don't use CPUState alpha hw/: Don't use CPUState xtensa-semi: Don't use CPUState m68k-semi: Don't use CPUState arm-semi: Don't use CPUState target-xtensa: Don't overuse CPUState target-unicore32: Don't overuse CPUState ...
Diffstat (limited to 'arm-semi.c')
| -rw-r--r-- | arm-semi.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arm-semi.c b/arm-semi.c index 873518a20e..8debd19e3a 100644 --- a/arm-semi.c +++ b/arm-semi.c @@ -108,7 +108,7 @@ static inline uint32_t set_swi_errno(TaskState *ts, uint32_t code) return code; } #else -static inline uint32_t set_swi_errno(CPUState *env, uint32_t code) +static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) { return code; } @@ -122,7 +122,7 @@ static target_ulong arm_semi_syscall_len; static target_ulong syscall_err; #endif -static void arm_semi_cb(CPUState *env, target_ulong ret, target_ulong err) +static void arm_semi_cb(CPUARMState *env, target_ulong ret, target_ulong err) { #ifdef CONFIG_USER_ONLY TaskState *ts = env->opaque; @@ -152,7 +152,7 @@ static void arm_semi_cb(CPUState *env, target_ulong ret, target_ulong err) } } -static void arm_semi_flen_cb(CPUState *env, target_ulong ret, target_ulong err) +static void arm_semi_flen_cb(CPUARMState *env, target_ulong ret, target_ulong err) { /* The size is always stored in big-endian order, extract the value. We assume the size always fit in 32 bits. */ @@ -174,7 +174,7 @@ static void arm_semi_flen_cb(CPUState *env, target_ulong ret, target_ulong err) __arg; \ }) #define SET_ARG(n, val) put_user_ual(val, args + (n) * 4) -uint32_t do_arm_semihosting(CPUState *env) +uint32_t do_arm_semihosting(CPUARMState *env) { target_ulong args; char * s; @@ -184,7 +184,7 @@ uint32_t do_arm_semihosting(CPUState *env) #ifdef CONFIG_USER_ONLY TaskState *ts = env->opaque; #else - CPUState *ts = env; + CPUARMState *ts = env; #endif nr = env->regs[0]; |