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| author | Paolo Bonzini <pbonzini@redhat.com> | 2018-12-13 23:37:36 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2019-01-11 15:46:55 +0100 |
| commit | 72e21db7ea7c0aa17f95c6871a827afe0f43ed24 (patch) | |
| tree | cfc86fb806948246bc50af26490f0950628b03ce /disas/alpha.c | |
| parent | 6afeb39713010742b4c45e2693ee7b3bf098fba8 (diff) | |
| download | focaccia-qemu-72e21db7ea7c0aa17f95c6871a827afe0f43ed24.tar.gz focaccia-qemu-72e21db7ea7c0aa17f95c6871a827afe0f43ed24.zip | |
remove space-tab sequences
There are not many, and they are all simple mistakes that ended up being committed. Remove them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20181213223737.11793-2-pbonzini@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'disas/alpha.c')
| -rw-r--r-- | disas/alpha.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/disas/alpha.c b/disas/alpha.c index b7b0ae0d92..a0c9ecd49d 100644 --- a/disas/alpha.c +++ b/disas/alpha.c @@ -672,7 +672,7 @@ extract_ev6hwjhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED) OPCODE is the instruction opcode. MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. + which bits in the actual opcode must match OPCODE. OPERANDS is the list of operands. @@ -699,10 +699,10 @@ extract_ev6hwjhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED) And two annotations: EV56 BUT opcodes that are officially introduced as of the ev56, - but with defined results on previous implementations. + but with defined results on previous implementations. EV56 UNA opcodes that were introduced as of the ev56 with - presumably undefined results on previous implementations + presumably undefined results on previous implementations that were not assigned to a particular extension. */ @@ -832,7 +832,7 @@ const struct alpha_opcode alpha_opcodes[] = { { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), - 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ + 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, |