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| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:08:02 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | 0ec8c4296d48efc0a9ee7ac7bdc7523b793de4bd (patch) | |
| tree | 1beca82f3f1bce08fe4e6d51d2e366709e579025 /docs/system | |
| parent | e2e9b9e129f484398326f262de2933a3db3f8c62 (diff) | |
| download | focaccia-qemu-0ec8c4296d48efc0a9ee7ac7bdc7523b793de4bd.tar.gz focaccia-qemu-0ec8c4296d48efc0a9ee7ac7bdc7523b793de4bd.zip | |
docs/system/arm/xlnx-versal-virt: update supported devices
Update the list of supported devices in the Versal SoCs. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-45-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs/system')
| -rw-r--r-- | docs/system/arm/xlnx-versal-virt.rst | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst index 2c63fbf519..94c8bacf61 100644 --- a/docs/system/arm/xlnx-versal-virt.rst +++ b/docs/system/arm/xlnx-versal-virt.rst @@ -23,11 +23,11 @@ limitations. Currently, we support the following cores and devices: Implemented CPU cores: -- 2 ACPUs (ARM Cortex-A72) +- 2 ACPUs (ARM Cortex-A72) with their GICv3 and ITS +- 2 RCPUs (ARM Cortex-R5F) with their GICv2 Implemented devices: -- Interrupt controller (ARM GICv3) - 2 UARTs (ARM PL011) - An RTC (Versal built-in) - 2 GEMs (Cadence MACB Ethernet MACs) @@ -39,6 +39,9 @@ Implemented devices: - BBRAM (36 bytes of Battery-backed RAM) - eFUSE (3072 bytes of one-time field-programmable bit array) - 2 CANFDs +- USB controller +- OSPI controller +- TRNG controller QEMU does not yet model any other devices, including the PL and the AI Engine. |