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| author | Cédric Le Goater <clg@kaod.org> | 2021-03-09 12:01:28 +0100 |
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| committer | Cédric Le Goater <clg@kaod.org> | 2021-03-09 12:01:28 +0100 |
| commit | 2ecf17264debe1bc3399fe587690c78d03e8401b (patch) | |
| tree | 792d6d3331647aff8e0d1e5a587b240bcb0d19dc /hw/arm/aspeed_soc.c | |
| parent | 6820588efa4fbab9ab6f0457f2c83c3bc7498ae3 (diff) | |
| download | focaccia-qemu-2ecf17264debe1bc3399fe587690c78d03e8401b.tar.gz focaccia-qemu-2ecf17264debe1bc3399fe587690c78d03e8401b.zip | |
hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-Id: <20210302014317.915120-5-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/arm/aspeed_soc.c')
| -rw-r--r-- | hw/arm/aspeed_soc.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 7eefd54ac0..4f098da437 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -211,6 +211,8 @@ static void aspeed_soc_init(Object *obj) object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); } + + object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); } static void aspeed_soc_realize(DeviceState *dev, Error **errp) @@ -393,6 +395,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) sc->memmap[ASPEED_DEV_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); + + /* LPC */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); } static Property aspeed_soc_properties[] = { DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, |