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| author | Jerome Forissier <jerome.forissier@linaro.org> | 2022-10-03 16:56:41 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-10-10 14:52:25 +0100 |
| commit | 0ff993193fe759b735e382fbe06b8258b537f95d (patch) | |
| tree | e4156ab4c65523ba485d2d6dba922e2450aea587 /hw/arm/boot.c | |
| parent | 7fa7ea8f480cd6f3f5f2a9453eea5733510b6c8b (diff) | |
| download | focaccia-qemu-0ff993193fe759b735e382fbe06b8258b537f95d.tar.gz focaccia-qemu-0ff993193fe759b735e382fbe06b8258b537f95d.zip | |
hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
According to the Linux kernel booting.rst [1], CPTR_EL3.ESM and
SCR_EL3.EnTP2 must be initialized to 1 when EL3 is present and FEAT_SME
is advertised. This has to be taken care of when QEMU boots directly
into the kernel (i.e., "-M virt,secure=on -cpu max -kernel Image").
Cc: qemu-stable@nongnu.org
Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max")
Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.rst?h=v6.0#n321
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Message-id: 20221003145641.1921467-1-jerome.forissier@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/boot.c')
| -rw-r--r-- | hw/arm/boot.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index ada2717f76..ee3858b673 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -763,6 +763,10 @@ static void do_cpu_reset(void *opaque) if (cpu_isar_feature(aa64_sve, cpu)) { env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; } + if (cpu_isar_feature(aa64_sme, cpu)) { + env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; + env->cp15.scr_el3 |= SCR_ENTP2; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: |