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| author | Shameer Kolothum <skolothumtho@nvidia.com> | 2025-08-29 09:25:29 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-09-16 17:31:54 +0100 |
| commit | 66d2f665e163cf1afccd171e3c16f8d3acb3d94a (patch) | |
| tree | cd80be63d14a49021e43e664d23b364dc1c9bfc6 /hw/arm/smmu-common.c | |
| parent | 951bc76fb669eab96cc60e38a50097ad4435163e (diff) | |
| download | focaccia-qemu-66d2f665e163cf1afccd171e3c16f8d3acb3d94a.tar.gz focaccia-qemu-66d2f665e163cf1afccd171e3c16f8d3acb3d94a.zip | |
hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation
Allow cold-plugging of an SMMUv3 device on the virt machine when no global (legacy) SMMUv3 is present or when a virtio-iommu is specified. This user-created SMMUv3 device is tied to a specific PCI bus provided by the user, so ensure the IOMMU ops are configured accordingly. Due to current limitations in QEMU’s device tree support, specifically its inability to properly present pxb-pcie based root complexes and their devices, the device tree support for the new SMMUv3 device is limited to cases where it is attached to the default pcie.0 root complex. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nathan Chen <nathanc@nvidia.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Message-id: 20250829082543.7680-8-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/smmu-common.c')
| -rw-r--r-- | hw/arm/smmu-common.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 7f64ea48d0..62a7612184 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -961,7 +961,12 @@ static void smmu_base_realize(DeviceState *dev, Error **errp) goto out_err; } } - pci_setup_iommu(pci_bus, &smmu_ops, s); + + if (s->smmu_per_bus) { + pci_setup_iommu_per_bus(pci_bus, &smmu_ops, s); + } else { + pci_setup_iommu(pci_bus, &smmu_ops, s); + } return; } out_err: @@ -986,6 +991,7 @@ static void smmu_base_reset_exit(Object *obj, ResetType type) static const Property smmu_dev_properties[] = { DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0), + DEFINE_PROP_BOOL("smmu_per_bus", SMMUState, smmu_per_bus, false), DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, TYPE_PCI_BUS, PCIBus *), }; |