Merge tag 'pull-target-arm-20250725' of https://gitlab.com/pm215/qemu into staging

target-arm queue:
 * Fix various bugs in SMEp/SVE2p1 load/store handling
 * hw/arm/smmu-common: Avoid using inlined functions with external linkage
 * target/arm: hvf: stubbing reads to LORC_EL1

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# gpg: Signature made Fri 25 Jul 2025 07:40:02 EDT
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# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20250725' of https://gitlab.com/pm215/qemu:
  target/arm: hvf: stubbing reads to LORC_EL1
  hw/arm/smmu-common: Avoid using inlined functions with external linkage
  target/arm: Fix LD1W, LD1D to 128-bit elements
  target/arm: Pass correct esize to sve_st1_z() for LD1Q, ST1Q
  target/arm: LD1Q, ST1Q are vector + scalar, not scalar + vector
  decodetree: Infer argument set before inferring format
  target/arm: Pack mtedesc into upper 32 bits of descriptor
  target/arm: Expand the descriptor for SME/SVE memory ops to i64

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index f39b99e526..0dcaf2f589 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -319,7 +319,7 @@ void smmu_iotlb_inv_vmid(SMMUState *s, int vmid)
     g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid, &vmid);
 }
 
-inline void smmu_iotlb_inv_vmid_s1(SMMUState *s, int vmid)
+void smmu_iotlb_inv_vmid_s1(SMMUState *s, int vmid)
 {
     trace_smmu_iotlb_inv_vmid_s1(vmid);
     g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid_s1, &vmid);