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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-12-30 17:02:42 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-12-30 17:02:42 -0800 |
| commit | 69f153667fce723ee546d2f047d66d0cfa67c3cc (patch) | |
| tree | a005491be410d7391e15f766680fb28d7acc4188 /hw/arm/smmuv3.c | |
| parent | d5a9f352896fe43183ef01072b374e89a3488315 (diff) | |
| parent | 4a63054bce23982b99f4d3c65528e47e614086b2 (diff) | |
| download | focaccia-qemu-69f153667fce723ee546d2f047d66d0cfa67c3cc.tar.gz focaccia-qemu-69f153667fce723ee546d2f047d66d0cfa67c3cc.zip | |
Merge tag 'memory-api-20211231' of https://github.com/philmd/qemu into staging
Memory API patches Have various functions from the Memory API: - take a MemTxAttrs argument, - propagate a MemTxResult. # gpg: Signature made Thu 30 Dec 2021 04:52:20 PM PST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'memory-api-20211231' of https://github.com/philmd/qemu: (22 commits) pci: Let ld*_pci_dma() propagate MemTxResult pci: Let st*_pci_dma() propagate MemTxResult pci: Let ld*_pci_dma() take MemTxAttrs argument pci: Let st*_pci_dma() take MemTxAttrs argument dma: Let ld*_dma() propagate MemTxResult dma: Let st*_dma() propagate MemTxResult dma: Let ld*_dma() take MemTxAttrs argument dma: Let st*_dma() take MemTxAttrs argument dma: Let dma_buf_rw() propagate MemTxResult dma: Let dma_buf_read() take MemTxAttrs argument dma: Let dma_buf_write() take MemTxAttrs argument dma: Let dma_buf_rw() take MemTxAttrs argument pci: Let pci_dma_rw() take MemTxAttrs argument dma: Have dma_buf_read() / dma_buf_write() take a void pointer dma: Have dma_buf_rw() take a void pointer dma: Let dma_memory_map() take MemTxAttrs argument dma: Let dma_memory_read/write() take MemTxAttrs argument dma: Let dma_memory_rw() take MemTxAttrs argument dma: Let dma_memory_rw_relaxed() take MemTxAttrs argument dma: Let dma_memory_set() take MemTxAttrs argument ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/arm/smmuv3.c')
| -rw-r--r-- | hw/arm/smmuv3.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 01b60bee49..3b43368be0 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -102,7 +102,8 @@ static inline MemTxResult queue_read(SMMUQueue *q, void *data) { dma_addr_t addr = Q_CONS_ENTRY(q); - return dma_memory_read(&address_space_memory, addr, data, q->entry_size); + return dma_memory_read(&address_space_memory, addr, data, q->entry_size, + MEMTXATTRS_UNSPECIFIED); } static MemTxResult queue_write(SMMUQueue *q, void *data) @@ -110,7 +111,8 @@ static MemTxResult queue_write(SMMUQueue *q, void *data) dma_addr_t addr = Q_PROD_ENTRY(q); MemTxResult ret; - ret = dma_memory_write(&address_space_memory, addr, data, q->entry_size); + ret = dma_memory_write(&address_space_memory, addr, data, q->entry_size, + MEMTXATTRS_UNSPECIFIED); if (ret != MEMTX_OK) { return ret; } @@ -285,7 +287,8 @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, trace_smmuv3_get_ste(addr); /* TODO: guarantee 64-bit single-copy atomicity */ - ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)); + ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf), + MEMTXATTRS_UNSPECIFIED); if (ret != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Cannot fetch pte at address=0x%"PRIx64"\n", addr); @@ -306,7 +309,8 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid, trace_smmuv3_get_cd(addr); /* TODO: guarantee 64-bit single-copy atomicity */ - ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)); + ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf), + MEMTXATTRS_UNSPECIFIED); if (ret != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Cannot fetch pte at address=0x%"PRIx64"\n", addr); @@ -411,7 +415,7 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)); /* TODO: guarantee 64-bit single-copy atomicity */ ret = dma_memory_read(&address_space_memory, l1ptr, &l1std, - sizeof(l1std)); + sizeof(l1std), MEMTXATTRS_UNSPECIFIED); if (ret != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Could not read L1PTR at 0X%"PRIx64"\n", l1ptr); |