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| author | Samuel Tardieu <sam@rfc1149.net> | 2024-01-06 19:15:03 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-01-09 14:42:40 +0000 |
| commit | 4a04655c6bdeb1043a4b7477f54f76a3d6a3ec59 (patch) | |
| tree | 04addc31b4a80f56c27f1da81107d4917f0e5fec /hw/arm/stellaris.c | |
| parent | 33995902b462cf1c4ba1177ee758713dd8d4ec0d (diff) | |
| download | focaccia-qemu-4a04655c6bdeb1043a4b7477f54f76a3d6a3ec59.tar.gz focaccia-qemu-4a04655c6bdeb1043a4b7477f54f76a3d6a3ec59.zip | |
hw/arm/socs: configure priority bits for existing SOCs
Update the number of priority bits for a number of existing SoCs according to their technical documentation: - STM32F100/F205/F405/L4x5: 4 bits - Stellaris (Sandstorm/Fury): 3 bits Signed-off-by: Samuel Tardieu <sam@rfc1149.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240106181503.1746200-4-sam@rfc1149.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/stellaris.c')
| -rw-r--r-- | hw/arm/stellaris.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 729a8bf569..d18b1144af 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -47,6 +47,7 @@ #define BP_GAMEPAD 0x04 #define NUM_IRQ_LINES 64 +#define NUM_PRIO_BITS 3 typedef const struct { const char *name; @@ -1067,6 +1068,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) nvic = qdev_new(TYPE_ARMV7M); qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); + qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); qdev_prop_set_bit(nvic, "enable-bitband", true); qdev_connect_clock_in(nvic, "cpuclk", |