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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-11-07 20:33:59 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-11-10 11:03:48 +0000 |
| commit | 509602eed4d5d51cb71911ffc9c5ecc1cd04db06 (patch) | |
| tree | 9fcb00d70beb3be6649041146bd3895a90d9b435 /hw/arm/stm32f205_soc.c | |
| parent | 604cef3e57eaeeef77074d78f6cf2eca1be11c62 (diff) | |
| download | focaccia-qemu-509602eed4d5d51cb71911ffc9c5ecc1cd04db06.tar.gz focaccia-qemu-509602eed4d5d51cb71911ffc9c5ecc1cd04db06.zip | |
hw/arm/armsse: Correct expansion MPC interrupt lines
We can use one MPC per SRAM bank, but we currently only wire the
IRQ from the first expansion MPC to the IRQ splitter. Fix that.
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201107193403.436146-2-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/stm32f205_soc.c')
0 files changed, 0 insertions, 0 deletions