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authorFelipe Balbi <balbi@kernel.org>2022-12-30 16:57:32 +0200
committerPeter Maydell <peter.maydell@linaro.org>2023-01-12 16:50:18 +0000
commit829da0dbe3112a78ab3e298222cd42e000e39c70 (patch)
tree31e6ec723ac79cd544372955e09020244795da84 /hw/arm/stm32f405_soc.c
parent3db29dcac23da85486704ef9e7a8e7217f7829cd (diff)
downloadfocaccia-qemu-829da0dbe3112a78ab3e298222cd42e000e39c70.tar.gz
focaccia-qemu-829da0dbe3112a78ab3e298222cd42e000e39c70.zip
hw/arm/stm32f405: correctly describe the memory layout
STM32F405 has 128K of SRAM and another 64K of CCM (Core-coupled
Memory) at a different base address. Correctly describe the memory
layout to give existing FW images a chance to run unmodified.

Reviewed-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Message-id: 20221230145733.200496-2-balbi@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/stm32f405_soc.c')
-rw-r--r--hw/arm/stm32f405_soc.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index c07947d9f8..cef23d7ee4 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -139,6 +139,14 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
     }
     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
 
+    memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE,
+                           &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm);
+
     armv7m = DEVICE(&s->armv7m);
     qdev_prop_set_uint32(armv7m, "num-irq", 96);
     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);