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| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:07:34 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | 176faad4bf7565966398df0d6e8cd05825dfceea (patch) | |
| tree | 913c444cfa13f1e44c30c932416c4a9b190f9ec5 /hw/arm/xlnx-versal.c | |
| parent | 060b809271f9d0d6205fe2232d0aead4a37fa0e7 (diff) | |
| download | focaccia-qemu-176faad4bf7565966398df0d6e8cd05825dfceea.tar.gz focaccia-qemu-176faad4bf7565966398df0d6e8cd05825dfceea.zip | |
hw/arm/xlnx-versal: rtc: refactor creation
Refactor the RTC device creation using the VersalMap structure. The sysbus IRQ output 0 (APB IRQ) is connected instead of the output 1 (addr error IRQ). This does not change the current behaviour since the RTC model does not implement those IRQs anyway. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-17-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/xlnx-versal.c')
| -rw-r--r-- | hw/arm/xlnx-versal.c | 40 |
1 files changed, 31 insertions, 9 deletions
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 7a97d5df6b..9b1e0d46f1 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -38,6 +38,7 @@ #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" #include "hw/nvram/xlnx-bbram.h" #include "hw/misc/xlnx-versal-trng.h" +#include "hw/rtc/xlnx-zynqmp-rtc.h" #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") @@ -123,6 +124,12 @@ typedef struct VersalMap { VersalSimplePeriphMap pmc_iou_slcr; VersalSimplePeriphMap bbram; VersalSimplePeriphMap trng; + + struct VersalRtcMap { + VersalSimplePeriphMap map; + int alarm_irq; + int second_irq; + } rtc; } VersalMap; static const VersalMap VERSAL_MAP = { @@ -167,6 +174,10 @@ static const VersalMap VERSAL_MAP = { .pmc_iou_slcr = { 0xf1060000, OR_IRQ(121, 0) }, .bbram = { 0xf11f0000, OR_IRQ(121, 1) }, .trng = { 0xf1230000, 141 }, + .rtc = { + { 0xf12a0000, OR_IRQ(121, 2) }, + .alarm_irq = 142, .second_irq = 143 + }, }; static const VersalMap *VERSION_TO_MAP[] = { @@ -762,25 +773,36 @@ static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic) qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]); } -static void versal_create_rtc(Versal *s, qemu_irq *pic) +static void versal_create_rtc(Versal *s, const struct VersalRtcMap *map) { SysBusDevice *sbd; MemoryRegion *mr; + g_autofree char *node; + const char compatible[] = "xlnx,zynqmp-rtc"; + const char interrupt_names[] = "alarm\0sec"; - object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc, - TYPE_XLNX_ZYNQMP_RTC); - sbd = SYS_BUS_DEVICE(&s->pmc.rtc); - sysbus_realize(sbd, &error_fatal); + sbd = SYS_BUS_DEVICE(qdev_new(TYPE_XLNX_ZYNQMP_RTC)); + object_property_add_child(OBJECT(s), "rtc", OBJECT(sbd)); + sysbus_realize_and_unref(sbd, &error_abort); mr = sysbus_mmio_get_region(sbd, 0); - memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr); + memory_region_add_subregion(&s->mr_ps, map->map.addr, mr); /* * TODO: Connect the ALARM and SECONDS interrupts once our RTC model * supports them. */ - sysbus_connect_irq(sbd, 1, - qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0)); + versal_sysbus_connect_irq(s, sbd, 0, map->map.irq); + + node = versal_fdt_add_simple_subnode(s, "/rtc", map->map.addr, 0x10000, + compatible, sizeof(compatible)); + qemu_fdt_setprop_cells(s->cfg.fdt, node, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, map->alarm_irq, + GIC_FDT_IRQ_FLAGS_LEVEL_HI, + GIC_FDT_IRQ_TYPE_SPI, map->second_irq, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop(s->cfg.fdt, node, "interrupt-names", + interrupt_names, sizeof(interrupt_names)); } static void versal_create_trng(Versal *s, const VersalSimplePeriphMap *map) @@ -1341,9 +1363,9 @@ static void versal_realize(DeviceState *dev, Error **errp) versal_create_bbram(s, &map->bbram); versal_create_trng(s, &map->trng); + versal_create_rtc(s, &map->rtc); versal_create_pmc_apb_irq_orgate(s, pic); - versal_create_rtc(s, pic); versal_create_crl(s, pic); versal_create_cfu(s, pic); versal_map_ddr(s); |