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| author | Moger, Babu <Babu.Moger@amd.com> | 2019-11-07 18:00:57 +0000 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2020-03-17 19:48:10 -0400 |
| commit | a16e8dbc043720abcb37fc7dca313e720b4e0f0c (patch) | |
| tree | 94172599489a44500be7b58990f0a6129ab92c94 /hw/core/cpu.c | |
| parent | c63938df0aaa307771214d1152d5e1ade3e3b730 (diff) | |
| download | focaccia-qemu-a16e8dbc043720abcb37fc7dca313e720b4e0f0c.tar.gz focaccia-qemu-a16e8dbc043720abcb37fc7dca313e720b4e0f0c.zip | |
i386: Add missing cpu feature bits in EPYC model
Adds the following missing CPUID bits:
perfctr-core : core performance counter extensions support. Enables the VM
to use extended performance counter support. It enables six
programmable counters instead of 4 counters.
clzero : instruction zeroes out the 64 byte cache line specified in RAX.
xsaveerptr : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
pointers.
ibpb : Indirect Branch Prediction Barrie.
xsaves : XSAVES, XRSTORS and IA32_XSS supported.
Depends on following kernel commits:
40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
52297436199d ("kvm: svm: Update svm_xsaves_supported")
These new features will be added in EPYC-v3. The -cpu help output after the change.
x86 EPYC-v1 AMD EPYC Processor
x86 EPYC-v2 AMD EPYC Processor (with IBPB)
x86 EPYC-v3 AMD EPYC Processor
Signed-off-by: Babu Moger <babu.moger@amd.com>
Message-Id: <157314965662.23828.3063243729449408327.stgit@naples-babu.amd.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'hw/core/cpu.c')
0 files changed, 0 insertions, 0 deletions