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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-09-18 12:55:27 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-09-18 12:55:27 +0100 |
| commit | 3bf1f5ec6a7ec8ee06c95bf308d213ebaa129ee0 (patch) | |
| tree | 30c2e51a383243a8d135465729a43b0c2745d94f /hw/core/loader.c | |
| parent | 16a1b6e97c2a2919fd296db4bea2f9da2ad3cc4d (diff) | |
| parent | 9c708c7f9fbb813a3fac02f2728e51e62f2f5ffc (diff) | |
| download | focaccia-qemu-3bf1f5ec6a7ec8ee06c95bf308d213ebaa129ee0.tar.gz focaccia-qemu-3bf1f5ec6a7ec8ee06c95bf308d213ebaa129ee0.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150918' into staging
MIPS patches 2015-09-18 Changes: * fixes for rdhwr, tlbwr, mtc0, recip.fmt, rsqrt.fmt and daui instructions * removal of MIPS_DEBUG code * use tcg_gen_extrh_i64_i32() * improve random tlb index generation in cpu_mips_get_random() * exception handling improvements to correctly restore icount # gpg: Signature made Fri 18 Sep 2015 12:15:28 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" * remotes/lalrae/tags/mips-20150918: target-mips: improve exception handling target-mips: correct MTC0 instruction on MIPS64 target-mips: add missing restriction in DAUI instruction target-mips: fix corner case in TLBWR causing QEMU to hang pic32: use LCG algorithm for generated random index of TLBWR instruction target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS target-mips: get rid of MIPS_DEBUG target-mips: Fix RDHWR on CP0.Count target-mips: remove wrong checks for recip.fmt and rsqrt.fmt target-mips: Use tcg_gen_extrh_i64_i32 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/core/loader.c')
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